riscv/rocket-chip
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rocketchip: use TL2 and AXI4 for memory subsytem

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This commit is contained in:
Wesley W. Terpstra
2016-11-03 21:31:26 -07:00
parent 9d77e34bee
commit 32fd11935c
8 changed files with 59 additions and 64 deletions
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6
src/main/scala/rocketchip/BaseTop.scala
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@@ -55,6 +55,8 @@ trait TopNetwork extends HasPeripheryParameters {
TLWidthWidget(p(SOCBusKey).beatBytes)(
TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
socBus.node))
var coreplexMem = Seq[TLOutwardNode]()
}
trait TopNetworkBundle extends HasPeripheryParameters {
@@ -70,7 +72,6 @@ trait TopNetworkModule extends HasPeripheryParameters {
} =>
implicit val p = outer.p
val coreplexMem : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem)
val coreplexSlave: Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.slave)
val coreplexDebug: DebugBusIO = Wire(outer.coreplex.module.io.debug)
val coreplexRtc : Bool = Wire(outer.coreplex.module.io.rtcTick)
@@ -98,6 +99,8 @@ trait DirectConnection {
socBus.node := coreplex.mmio
coreplex.mmioInt := intBus.intnode
coreplexMem = coreplex.mem
}
trait DirectConnectionModule {
@@ -105,7 +108,6 @@ trait DirectConnectionModule {
val outer: BaseTop[BaseCoreplex]
} =>
coreplexMem <> outer.coreplex.module.io.mem
outer.coreplex.module.io.slave <> coreplexSlave
outer.coreplex.module.io.debug <> coreplexDebug
}