rocketchip: use TL2 and AXI4 for memory subsytem

src/main/scala/groundtest/Coreplex.scala

@@ -5,6 +5,7 @@ import cde.{Parameters}
 import coreplex._
 
 class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
+    with BroadcastL2
     with DirectConnection {
   override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
 }