riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

[tilelink2] Fix zero-width wires in RAMModel.

Browse Source
This commit is contained in:
Henry Cook 2016-09-28 16:52:08 -07:00 committed by Henry Cook
parent 69e121260e
commit 32f3f94882
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/tilelink2/RAMModel.scala
View File

@ -43,7 +43,7 @@ class TLRAMModel extends LazyModule
val endAddressHi = (endAddress / beatBytes).intValue
val maxLgBeats = log2Up(maxTransfer/beatBytes)
val shift = log2Ceil(beatBytes)
val decTrees = log2Ceil(maxTransfer/beatBytes)
val decTrees = log2Up(maxTransfer/beatBytes)
val addressBits = log2Up(endAddress)
val countBits = log2Up(endSourceId)
val sizeBits = edge.bundle.sizeBits