From 32f3f94882579643b06ba916fb08c8703e3c3666 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 28 Sep 2016 16:52:08 -0700 Subject: [PATCH] [tilelink2] Fix zero-width wires in RAMModel. --- src/main/scala/uncore/tilelink2/RAMModel.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/RAMModel.scala b/src/main/scala/uncore/tilelink2/RAMModel.scala index ba829574..533f6639 100644 --- a/src/main/scala/uncore/tilelink2/RAMModel.scala +++ b/src/main/scala/uncore/tilelink2/RAMModel.scala @@ -43,7 +43,7 @@ class TLRAMModel extends LazyModule val endAddressHi = (endAddress / beatBytes).intValue val maxLgBeats = log2Up(maxTransfer/beatBytes) val shift = log2Ceil(beatBytes) - val decTrees = log2Ceil(maxTransfer/beatBytes) + val decTrees = log2Up(maxTransfer/beatBytes) val addressBits = log2Up(endAddress) val countBits = log2Up(endSourceId) val sizeBits = edge.bundle.sizeBits