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[tilelink2] Fix zero-width wires in RAMModel.

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Henry Cook 2016-09-28 16:52:08 -07:00 committed by Henry Cook
parent 69e121260e
commit 32f3f94882
1 changed files with 1 additions and 1 deletions
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src/main/scala/uncore/tilelink2/RAMModel.scala
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@ -43,7 +43,7 @@ class TLRAMModel extends LazyModule
val endAddressHi = (endAddress / beatBytes).intValue val endAddressHi = (endAddress / beatBytes).intValue
val maxLgBeats = log2Up(maxTransfer/beatBytes) val maxLgBeats = log2Up(maxTransfer/beatBytes)
val shift = log2Ceil(beatBytes) val shift = log2Ceil(beatBytes)
val decTrees = log2Ceil(maxTransfer/beatBytes) val decTrees = log2Up(maxTransfer/beatBytes)
val addressBits = log2Up(endAddress) val addressBits = log2Up(endAddress)
val countBits = log2Up(endSourceId) val countBits = log2Up(endSourceId)
val sizeBits = edge.bundle.sizeBits val sizeBits = edge.bundle.sizeBits