riscv/rocket-chip
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fix -1:0 index problem for direct map case

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This commit is contained in:
Yunsup Lee 2012-03-26 17:00:01 -07:00
parent e2fe525fb6
commit 32d95e9594
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/icache.scala
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@ -81,7 +81,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
} }
val refill_done = io.mem.xact_rep.valid && refill_count.andR val refill_done = io.mem.xact_rep.valid && refill_count.andR
val repl_way = LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2up(assoc)-1,0) val repl_way = if (assoc == 1) UFix(0) else LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2up(assoc)-1,0)
val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix
val tag_we = refill_done val tag_we = refill_done
val tag_addr = val tag_addr =