From 32d95e9594aa90a382e081bedf060a3e61ea5884 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Mon, 26 Mar 2012 17:00:01 -0700 Subject: [PATCH] fix -1:0 index problem for direct map case --- rocket/src/main/scala/icache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index b1178f97..79ee7a23 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -81,7 +81,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component { } val refill_done = io.mem.xact_rep.valid && refill_count.andR - val repl_way = LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2up(assoc)-1,0) + val repl_way = if (assoc == 1) UFix(0) else LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2up(assoc)-1,0) val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix val tag_we = refill_done val tag_addr =