Merge pull request #1245 from freechipsproject/rv32d
Support fLen > xLen
This commit is contained in:
commit
32c5c3c04d
@ -165,8 +165,8 @@ class WithRV32 extends Config((site, here, up) => {
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case XLen => 32
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case XLen => 32
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(
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r.copy(core = r.core.copy(
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mulDiv = Some(MulDivParams(mulUnroll = 8)),
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fpu = r.core.fpu.map(_.copy(fLen = 32)),
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fpu = r.core.fpu.map(_.copy(divSqrt = false))))
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mulDiv = Some(MulDivParams(mulUnroll = 8))))
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}
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}
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})
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})
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@ -7,7 +7,6 @@ import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.rocket.Instructions
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import freechips.rocketchip.rocket.Instructions
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import freechips.rocketchip.tile.XLen
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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@ -424,7 +423,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
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}
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}
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}
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}
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class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: Parameters) extends LazyModule
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class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule
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{
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{
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val dmiNode = TLRegisterNode(
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val dmiNode = TLRegisterNode(
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@ -438,7 +437,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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val tlNode = TLRegisterNode(
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val tlNode = TLRegisterNode(
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address=Seq(AddressSet(0, 0xFFF)), // This is required for correct functionality, it's not configurable.
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address=Seq(AddressSet(0, 0xFFF)), // This is required for correct functionality, it's not configurable.
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device=device,
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device=device,
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beatBytes=p(XLen)/8,
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beatBytes=beatBytes,
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executable=true
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executable=true
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)
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)
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@ -1029,9 +1028,9 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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// Handles the synchronization of dmactive, which is used as a synchronous reset
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// Handles the synchronization of dmactive, which is used as a synchronous reset
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// inside the Inner block.
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// inside the Inner block.
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// Also is the Sink side of hartsel & resumereq fields of DMCONTROL.
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// Also is the Sink side of hartsel & resumereq fields of DMCONTROL.
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class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implicit p: Parameters) extends LazyModule{
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class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{
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val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents))
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val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes))
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val dmiXing = LazyModule(new TLAsyncCrossingSink(depth=1))
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val dmiXing = LazyModule(new TLAsyncCrossingSink(depth=1))
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val dmiNode = dmiXing.node
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val dmiNode = dmiXing.node
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val tlNode = dmInner.tlNode
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val tlNode = dmInner.tlNode
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@ -1060,14 +1059,14 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
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* because the Clock must run when tlClock isn't running or tlReset is asserted.
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* because the Clock must run when tlClock isn't running or tlReset is asserted.
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*/
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*/
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class TLDebugModule(implicit p: Parameters) extends LazyModule {
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class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
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val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){
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val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){
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override val alwaysExtended = true
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override val alwaysExtended = true
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}
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}
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val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p))
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val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p))
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val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size})(p))
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val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p))
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val node = dmInner.tlNode
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val node = dmInner.tlNode
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val intnode = dmOuter.intnode
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val intnode = dmOuter.intnode
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@ -29,7 +29,7 @@ class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with
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trait HasPeripheryDebug extends HasPeripheryBus {
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trait HasPeripheryDebug extends HasPeripheryBus {
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val module: HasPeripheryDebugModuleImp
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val module: HasPeripheryDebugModuleImp
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val debug = LazyModule(new TLDebugModule())
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val debug = LazyModule(new TLDebugModule(pbus.beatBytes))
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debug.node := pbus.toVariableWidthSlaves
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debug.node := pbus.toVariableWidthSlaves
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}
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}
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@ -7,7 +7,6 @@ import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex.HasPeripheryBus
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import freechips.rocketchip.coreplex.HasPeripheryBus
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tile.XLen
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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@ -33,7 +32,7 @@ case class ClintParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
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case object ClintKey extends Field(ClintParams())
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case object ClintKey extends Field(ClintParams())
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class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) extends LazyModule
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class CoreplexLocalInterrupter(params: ClintParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
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{
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{
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import ClintConsts._
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import ClintConsts._
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@ -45,7 +44,7 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
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val node = TLRegisterNode(
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val node = TLRegisterNode(
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address = Seq(params.address),
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address = Seq(params.address),
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device = device,
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device = device,
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beatBytes = p(XLen)/8)
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beatBytes = beatBytes)
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val intnode = IntNexusNode(
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val intnode = IntNexusNode(
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sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
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sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
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@ -93,6 +92,6 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
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/** Trait that will connect a Clint to a coreplex */
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/** Trait that will connect a Clint to a coreplex */
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trait HasPeripheryClint extends HasPeripheryBus {
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trait HasPeripheryClint extends HasPeripheryBus {
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val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey)))
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val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey), pbus.beatBytes))
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clint.node := pbus.toVariableWidthSlaves
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clint.node := pbus.toVariableWidthSlaves
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}
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}
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@ -8,7 +8,6 @@ import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex.{HasInterruptBus, HasPeripheryBus}
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import freechips.rocketchip.coreplex.{HasInterruptBus, HasPeripheryBus}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tile.XLen
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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@ -64,7 +63,7 @@ case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, i
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case object PLICKey extends Field(PLICParams())
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case object PLICKey extends Field(PLICParams())
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/** Platform-Level Interrupt Controller */
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/** Platform-Level Interrupt Controller */
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class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
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{
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{
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// plic0 => max devices 1023
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// plic0 => max devices 1023
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val device = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
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val device = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
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@ -83,7 +82,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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val node = TLRegisterNode(
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val node = TLRegisterNode(
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address = Seq(params.address),
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address = Seq(params.address),
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device = device,
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device = device,
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beatBytes = p(XLen)/8,
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beatBytes = beatBytes,
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undefZero = true,
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undefZero = true,
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concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
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concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
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@ -271,7 +270,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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/** Trait that will connect a PLIC to a coreplex */
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/** Trait that will connect a PLIC to a coreplex */
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trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
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trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
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val plic = LazyModule(new TLPLIC(p(PLICKey)))
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val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes))
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plic.node := pbus.toVariableWidthSlaves
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plic.node := pbus.toVariableWidthSlaves
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plic.intnode := ibus.toPLIC
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plic.intnode := ibus.toPLIC
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}
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}
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@ -333,8 +333,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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val isaMaskString =
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val isaMaskString =
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(if (usingMulDiv) "M" else "") +
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(if (usingMulDiv) "M" else "") +
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(if (usingAtomics) "A" else "") +
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(if (usingAtomics) "A" else "") +
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(if (usingFPU) "F" else "") +
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(if (fLen >= 32) "F" else "") +
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(if (usingFPU && xLen > 32) "D" else "") +
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(if (fLen >= 64) "D" else "") +
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(if (usingCompressed) "C" else "") +
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(if (usingCompressed) "C" else "") +
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(if (usingRoCC) "X" else "")
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(if (usingRoCC) "X" else "")
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val isaString = "I" + isaMaskString +
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val isaString = "I" + isaMaskString +
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@ -687,7 +687,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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// AMOs
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// AMOs
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if (usingRMW) {
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if (usingRMW) {
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val amoalu = Module(new AMOALU(xLen))
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// when xLen < coreDataBits (e.g. RV32D), this AMOALU is wider than necessary
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val amoalu = Module(new AMOALU(coreDataBits))
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amoalu.io.mask := pstore1_mask
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amoalu.io.mask := pstore1_mask
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amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR)
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amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR)
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amoalu.io.lhs := s2_data_word
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amoalu.io.lhs := s2_data_word
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@ -46,8 +46,8 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParamet
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val cacheParams = tileParams.dcache.get
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val cacheParams = tileParams.dcache.get
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val cfg = cacheParams
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val cfg = cacheParams
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def wordBits = xLen // really, xLen max
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def wordBits = coreDataBits
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def wordBytes = wordBits/8
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def wordBytes = coreDataBytes
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def wordOffBits = log2Up(wordBytes)
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def wordOffBits = log2Up(wordBytes)
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def beatBytes = cacheBlockBytes / cacheDataBeats
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def beatBytes = cacheBlockBytes / cacheDataBeats
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def beatWords = beatBytes / wordBytes
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def beatWords = beatBytes / wordBytes
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@ -108,8 +108,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val decode_table = {
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val decode_table = {
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(if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++:
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(if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++:
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(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
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(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
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(if (usingFPU) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
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(if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
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(if (usingFPU && xLen > 32) Seq(new DDecode, new D64Decode) else Nil) ++:
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(if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:
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(usingRoCC.option(new RoCCDecode)) ++:
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(usingRoCC.option(new RoCCDecode)) ++:
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((xLen > 32).option(new I64Decode)) ++:
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((xLen > 32).option(new I64Decode)) ++:
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(usingVM.option(new SDecode)) ++:
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(usingVM.option(new SDecode)) ++:
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@ -250,8 +250,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses)
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coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses)
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val dcache_bypass_data =
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val dcache_bypass_data =
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if (fastLoadByte) io.dmem.resp.bits.data
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if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0)
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else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass
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else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0)
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else wb_reg_wdata
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else wb_reg_wdata
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// detect bypass opportunities
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// detect bypass opportunities
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@ -527,7 +527,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val wb_wen = wb_valid && wb_ctrl.wxd
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val wb_wen = wb_valid && wb_ctrl.wxd
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val rf_wen = wb_wen || ll_wen
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val rf_wen = wb_wen || ll_wen
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val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
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val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
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val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data,
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val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0),
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Mux(ll_wen, ll_wdata,
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Mux(ll_wen, ll_wdata,
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Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
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Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
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wb_reg_wdata)))
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wb_reg_wdata)))
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@ -676,7 +676,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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io.dmem.req.bits.phys := Bool(false)
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io.dmem.req.bits.phys := Bool(false)
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io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
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io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
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io.dmem.invalidate_lr := wb_xcpt
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io.dmem.invalidate_lr := wb_xcpt
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io.dmem.s1_data.data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
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io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill((xLen max fLen) / fLen, io.fpu.store_data), mem_reg_rs2))
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io.dmem.s1_kill := killm_common || mem_breakpoint
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io.dmem.s1_kill := killm_common || mem_breakpoint
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io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
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io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
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@ -57,15 +57,14 @@ object Generator extends GeneratorApp {
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val env = if (vm) List("p","v") else List("p")
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val env = if (vm) List("p","v") else List("p")
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coreParams.fpu foreach { case cfg =>
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coreParams.fpu foreach { case cfg =>
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if (xlen == 32) {
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if (xlen == 32) {
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TestGeneration.addSuites(env.map(rv32ufNoDiv))
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TestGeneration.addSuites(env.map(rv32uf))
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if (cfg.fLen >= 64)
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TestGeneration.addSuites(env.map(rv32ud))
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} else {
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} else {
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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if (cfg.fLen >= 64)
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if (cfg.divSqrt) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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TestGeneration.addSuites(env.map(rv64ud))
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}
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}
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}
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}
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}
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if (coreParams.useAtomics) {
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if (coreParams.useAtomics) {
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@ -143,13 +143,12 @@ object DefaultTestSuites {
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val rv64ufNames = LinkedHashSet("ldst", "move", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd")
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val rv64ufNames = LinkedHashSet("ldst", "move", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd")
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val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
|
val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
|
||||||
val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", rv64ufNames - "fdiv")(_)
|
|
||||||
|
|
||||||
val rv32ufNoDiv = new AssemblyTestSuite("rv32uf", rv64ufNames - "fdiv")(_)
|
val rv32uf = new AssemblyTestSuite("rv32uf", rv64ufNames)(_)
|
||||||
|
val rv32ud = new AssemblyTestSuite("rv32ud", rv64ufNames - "move")(_)
|
||||||
|
|
||||||
val rv64udNames = rv64ufNames + "structural"
|
val rv64udNames = rv64ufNames + "structural"
|
||||||
val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_)
|
val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_)
|
||||||
val rv64udNoDiv = new AssemblyTestSuite("rv64ud", rv64udNames - "fdiv")(_)
|
|
||||||
|
|
||||||
val rv64siNames = rv32siNames
|
val rv64siNames = rv32siNames
|
||||||
val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_)
|
val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_)
|
||||||
|
@ -44,7 +44,7 @@ trait CoreParams {
|
|||||||
trait HasCoreParameters extends HasTileParameters {
|
trait HasCoreParameters extends HasTileParameters {
|
||||||
val coreParams: CoreParams = tileParams.core
|
val coreParams: CoreParams = tileParams.core
|
||||||
|
|
||||||
val fLen = xLen // TODO relax this
|
val fLen = coreParams.fpu.map(_.fLen).getOrElse(0)
|
||||||
|
|
||||||
val usingMulDiv = coreParams.mulDiv.nonEmpty
|
val usingMulDiv = coreParams.mulDiv.nonEmpty
|
||||||
val usingFPU = coreParams.fpu.nonEmpty
|
val usingFPU = coreParams.fpu.nonEmpty
|
||||||
|
@ -14,6 +14,7 @@ import freechips.rocketchip.util.property._
|
|||||||
import chisel3.internal.sourceinfo.SourceInfo
|
import chisel3.internal.sourceinfo.SourceInfo
|
||||||
|
|
||||||
case class FPUParams(
|
case class FPUParams(
|
||||||
|
fLen: Int = 64,
|
||||||
divSqrt: Boolean = true,
|
divSqrt: Boolean = true,
|
||||||
sfmaLatency: Int = 3,
|
sfmaLatency: Int = 3,
|
||||||
dfmaLatency: Int = 4
|
dfmaLatency: Int = 4
|
||||||
@ -168,6 +169,12 @@ class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
|
|||||||
val exc = Bits(width = FPConstants.FLAGS_SZ)
|
val exc = Bits(width = FPConstants.FLAGS_SZ)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
|
||||||
|
val rm = Bits(width = FPConstants.RM_SZ)
|
||||||
|
val typ = Bits(width = 2)
|
||||||
|
val in1 = Bits(width = xLen)
|
||||||
|
}
|
||||||
|
|
||||||
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
|
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
|
||||||
val rm = Bits(width = FPConstants.RM_SZ)
|
val rm = Bits(width = FPConstants.RM_SZ)
|
||||||
val fmaCmd = Bits(width = 2)
|
val fmaCmd = Bits(width = 2)
|
||||||
@ -233,6 +240,7 @@ object FType {
|
|||||||
}
|
}
|
||||||
|
|
||||||
trait HasFPUParameters {
|
trait HasFPUParameters {
|
||||||
|
require(fLen == 32 || fLen == 64)
|
||||||
val fLen: Int
|
val fLen: Int
|
||||||
def xLen: Int
|
def xLen: Int
|
||||||
val minXLen = 32
|
val minXLen = 32
|
||||||
@ -390,7 +398,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
|
|||||||
val store = ieee(in.in1)
|
val store = ieee(in.in1)
|
||||||
val toint = Wire(init = store)
|
val toint = Wire(init = store)
|
||||||
val intType = Wire(init = tag)
|
val intType = Wire(init = tag)
|
||||||
io.out.bits.store := ((0 until nIntTypes).map(i => Fill(1 << (nIntTypes - i - 1), store((minXLen << i) - 1, 0))): Seq[UInt])(tag)
|
io.out.bits.store := (floatTypes.map(t => Fill(maxType.ieeeWidth / t.ieeeWidth, store(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
|
||||||
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
|
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
|
||||||
io.out.bits.exc := Bits(0)
|
io.out.bits.exc := Bits(0)
|
||||||
|
|
||||||
@ -441,7 +449,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
|
|||||||
|
|
||||||
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
|
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
|
||||||
val io = new Bundle {
|
val io = new Bundle {
|
||||||
val in = Valid(new FPInput).flip
|
val in = Valid(new IntToFPInput).flip
|
||||||
val out = Valid(new FPResult)
|
val out = Valid(new FPResult)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user