riscv/rocket-chip
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Use Chisel3 SeqMem construct

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This commit is contained in:
Andrew Waterman 2015-07-11 13:32:45 -07:00
parent 5ed2899e56
commit 3233867390
2 changed files with 16 additions and 22 deletions
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30
rocket/src/main/scala/icache.scala
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@ -196,17 +196,13 @@ class ICache extends FrontendModule
val repl_way = if (isDM) UInt(0) else LFSR16(s2_miss)(log2Up(nWays)-1,0) val repl_way = if (isDM) UInt(0) else LFSR16(s2_miss)(log2Up(nWays)-1,0)
val entagbits = code.width(tagBits) val entagbits = code.width(tagBits)
val tag_array = Mem(Bits(width = entagbits*nWays), nSets, seqRead = true) val tag_array = SeqMem(Bits(width = entagbits*nWays), nSets)
val tag_raddr = Reg(UInt()) val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid)
when (refill_done) { when (refill_done) {
val wmask = FillInterleaved(entagbits, if (isDM) Bits(1) else UIntToOH(repl_way)) val wmask = FillInterleaved(entagbits, if (isDM) Bits(1) else UIntToOH(repl_way))
val tag = code.encode(s2_tag).toUInt val tag = code.encode(s2_tag).toUInt
tag_array.write(s2_idx, Fill(nWays, tag), wmask) tag_array.write(s2_idx, Fill(nWays, tag), wmask)
} }
// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
.elsewhen (s0_valid) {
tag_raddr := s0_pgoff(untagBits-1,blockOffBits)
}
val vb_array = Reg(init=Bits(0, nSets*nWays)) val vb_array = Reg(init=Bits(0, nSets*nWays))
when (refill_done && !invalidated) { when (refill_done && !invalidated) {
@ -229,7 +225,7 @@ class ICache extends FrontendModule
val s2_vb = Reg(Bool()) val s2_vb = Reg(Bool())
val s2_tag_disparity = Reg(Bool()) val s2_tag_disparity = Reg(Bool())
val s2_tag_match = Reg(Bool()) val s2_tag_match = Reg(Bool())
val tag_out = tag_array(tag_raddr)(entagbits*(i+1)-1, entagbits*i) val tag_out = tag_rdata(entagbits*(i+1)-1, entagbits*i)
when (s1_valid && rdy && !stall) { when (s1_valid && rdy && !stall) {
s2_vb := s1_vb s2_vb := s1_vb
s2_tag_disparity := code.decode(tag_out).error s2_tag_disparity := code.decode(tag_out).error
@ -242,19 +238,17 @@ class ICache extends FrontendModule
s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_) s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
for (i <- 0 until nWays) { for (i <- 0 until nWays) {
val data_array = Mem(Bits(width = code.width(rowBits)), nSets*refillCycles, seqRead = true) val data_array = SeqMem(Bits(width = code.width(rowBits)), nSets*refillCycles)
val s1_raddr = Reg(UInt()) val wen = narrow_grant.valid && repl_way === UInt(i)
when (narrow_grant.valid && repl_way === UInt(i)) { when (wen) {
val e_d = code.encode(narrow_grant.bits.data) val e_d = code.encode(narrow_grant.bits.data).toUInt
if(refillCycles > 1) data_array(Cat(s2_idx, refill_cnt)) := e_d if(refillCycles > 1) data_array.write(Cat(s2_idx, refill_cnt), e_d)
else data_array(s2_idx) := e_d else data_array.write(s2_idx, e_d)
}
// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
.elsewhen (s0_valid) {
s1_raddr := s0_pgoff(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0))
} }
val s0_raddr = s0_pgoff(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0))
val s1_rdata = data_array.read(s0_raddr, !wen && s0_valid)
// if s1_tag_match is critical, replace with partial tag check // if s1_tag_match is critical, replace with partial tag check
when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) } when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s2_dout(i) := s1_rdata }
} }
val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(rowBytes)-1,log2Up(coreInstBytes)) << log2Up(coreInstBits)))(coreInstBits-1,0)) val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(rowBytes)-1,log2Up(coreInstBytes)) << log2Up(coreInstBits)))(coreInstBits-1,0))
io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word) io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)

8
rocket/src/main/scala/nbdcache.scala
View File

@ -551,13 +551,13 @@ class DataArray extends L1HellaCacheModule {
val resp = Vec.fill(rowWords){Bits(width = encRowBits)} val resp = Vec.fill(rowWords){Bits(width = encRowBits)}
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid) val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
for (p <- 0 until resp.size) { for (p <- 0 until resp.size) {
val array = Mem(Bits(width=encRowBits), nSets*refillCycles, seqRead = true) val array = SeqMem(Bits(width=encRowBits), nSets*refillCycles)
when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) { when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
val data = Fill(rowWords, io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p)) val data = Fill(rowWords, io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
val mask = FillInterleaved(encDataBits, wway_en) val mask = FillInterleaved(encDataBits, wway_en)
array.write(waddr, data, mask) array.write(waddr, data, mask)
} }
resp(p) := array(RegEnable(raddr, rway_en.orR && io.read.valid)) resp(p) := array.read(raddr, rway_en.orR && io.read.valid)
} }
for (dw <- 0 until rowWords) { for (dw <- 0 until rowWords) {
val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw))) val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw)))
@ -570,11 +570,11 @@ class DataArray extends L1HellaCacheModule {
} else { } else {
val wmask = FillInterleaved(encDataBits, io.write.bits.wmask) val wmask = FillInterleaved(encDataBits, io.write.bits.wmask)
for (w <- 0 until nWays) { for (w <- 0 until nWays) {
val array = Mem(Bits(width=encRowBits), nSets*refillCycles, seqRead = true) val array = SeqMem(Bits(width=encRowBits), nSets*refillCycles)
when (io.write.bits.way_en(w) && io.write.valid) { when (io.write.bits.way_en(w) && io.write.valid) {
array.write(waddr, io.write.bits.data, wmask) array.write(waddr, io.write.bits.data, wmask)
} }
io.resp(w) := array(RegEnable(raddr, io.read.bits.way_en(w) && io.read.valid)) io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid)
} }
} }