riscv/rocket-chip
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Removed all traces of params

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This commit is contained in:
Henry Cook 2015-10-05 21:41:46 -07:00
parent 908922c1a4
commit 31be6407ec
11 changed files with 456 additions and 425 deletions
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33
uncore/src/main/scala/broadcast.scala
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@ -5,19 +5,20 @@ import Chisel._
case object L2StoreDataQueueDepth extends Field[Int] case object L2StoreDataQueueDepth extends Field[Int]
trait BroadcastHubParameters extends CoherenceAgentParameters { trait HasBroadcastHubParameters extends HasCoherenceAgentParameters {
val sdqDepth = params(L2StoreDataQueueDepth)*innerDataBeats val sdqDepth = p(L2StoreDataQueueDepth)*innerDataBeats
val dqIdxBits = math.max(log2Up(nReleaseTransactors) + 1, log2Up(sdqDepth)) val dqIdxBits = math.max(log2Up(nReleaseTransactors) + 1, log2Up(sdqDepth))
val nDataQueueLocations = 3 //Stores, VoluntaryWBs, Releases val nDataQueueLocations = 3 //Stores, VoluntaryWBs, Releases
} }
class DataQueueLocation extends Bundle with BroadcastHubParameters { class DataQueueLocation(implicit p: Parameters) extends CoherenceAgentBundle()(p)
with HasBroadcastHubParameters {
val idx = UInt(width = dqIdxBits) val idx = UInt(width = dqIdxBits)
val loc = UInt(width = log2Ceil(nDataQueueLocations)) val loc = UInt(width = log2Ceil(nDataQueueLocations))
} }
object DataQueueLocation { object DataQueueLocation {
def apply(idx: UInt, loc: UInt) = { def apply(idx: UInt, loc: UInt)(implicit p: Parameters) = {
val d = Wire(new DataQueueLocation) val d = Wire(new DataQueueLocation)
d.idx := idx d.idx := idx
d.loc := loc d.loc := loc
@ -25,12 +26,12 @@ object DataQueueLocation {
} }
} }
class L2BroadcastHub extends ManagerCoherenceAgent class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
with BroadcastHubParameters { with HasBroadcastHubParameters {
val internalDataBits = new DataQueueLocation().getWidth val internalDataBits = new DataQueueLocation().getWidth
val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations) val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations)
val trackerTLParams = params.alterPartial({ val trackerTLParams = p.alterPartial({
case TLDataBits => internalDataBits case TLDataBits => internalDataBits
case TLWriteMaskBits => innerWriteMaskBits case TLWriteMaskBits => innerWriteMaskBits
}) })
@ -104,10 +105,10 @@ class L2BroadcastHub extends ManagerCoherenceAgent
doInputRouting(io.inner.finish, trackerList.map(_.io.inner.finish)) doInputRouting(io.inner.finish, trackerList.map(_.io.inner.finish))
// Create an arbiter for the one memory port // Create an arbiter for the one memory port
val outer_arb = Module(new ClientUncachedTileLinkIOArbiter(trackerList.size), val outer_arb = Module(new ClientUncachedTileLinkIOArbiter(trackerList.size)(p.alterPartial(
{ case TLId => params(OuterTLId) { case TLId => p(OuterTLId)
case TLDataBits => internalDataBits case TLDataBits => internalDataBits
case TLWriteMaskBits => innerWriteMaskBits }) case TLWriteMaskBits => innerWriteMaskBits })))
outer_arb.io.in <> trackerList.map(_.io.outer) outer_arb.io.in <> trackerList.map(_.io.outer)
// Get the pending data out of the store data queue // Get the pending data out of the store data queue
val outer_data_ptr = new DataQueueLocation().fromBits(outer_arb.io.out.acquire.bits.data) val outer_data_ptr = new DataQueueLocation().fromBits(outer_arb.io.out.acquire.bits.data)
@ -127,15 +128,16 @@ class L2BroadcastHub extends ManagerCoherenceAgent
} }
} }
class BroadcastXactTracker extends XactTracker { class BroadcastXactTracker(implicit p: Parameters) extends XactTracker()(p) {
val io = new ManagerXactTrackerIO val io = new ManagerXactTrackerIO
} }
class BroadcastVoluntaryReleaseTracker(trackerId: Int) extends BroadcastXactTracker { class BroadcastVoluntaryReleaseTracker(trackerId: Int)
(implicit p: Parameters) extends BroadcastXactTracker()(p) {
val s_idle :: s_outer :: s_grant :: s_ack :: Nil = Enum(UInt(), 4) val s_idle :: s_outer :: s_grant :: s_ack :: Nil = Enum(UInt(), 4)
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 })) val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => p(InnerTLId); case TLDataBits => 0 }))
val data_buffer = Reg(Vec(io.irel().data, innerDataBeats)) val data_buffer = Reg(Vec(io.irel().data, innerDataBeats))
val coh = ManagerMetadata.onReset val coh = ManagerMetadata.onReset
@ -210,12 +212,13 @@ class BroadcastVoluntaryReleaseTracker(trackerId: Int) extends BroadcastXactTrac
} }
} }
class BroadcastAcquireTracker(trackerId: Int) extends BroadcastXactTracker { class BroadcastAcquireTracker(trackerId: Int)
(implicit p: Parameters) extends BroadcastXactTracker()(p) {
val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_mem_resp :: s_ack :: Nil = Enum(UInt(), 7) val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_mem_resp :: s_ack :: Nil = Enum(UInt(), 7)
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(Bundle(new AcquireFromSrc, { val xact = Reg(Bundle(new AcquireFromSrc, {
case TLId => params(InnerTLId) case TLId => p(InnerTLId)
case TLDataBits => 0 case TLDataBits => 0
case TLWriteMaskBits => innerWriteMaskBits case TLWriteMaskBits => innerWriteMaskBits
})) }))

161
uncore/src/main/scala/cache.scala
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@ -18,23 +18,26 @@ case object CacheBlockBytes extends Field[Int]
case object CacheBlockOffsetBits extends Field[Int] case object CacheBlockOffsetBits extends Field[Int]
case object ECCCode extends Field[Option[Code]] case object ECCCode extends Field[Option[Code]]
abstract trait CacheParameters extends UsesParameters { trait HasCacheParameters {
val nSets = params(NSets) implicit val p: Parameters
val blockOffBits = params(CacheBlockOffsetBits) val nSets = p(NSets)
val blockOffBits = p(CacheBlockOffsetBits)
val idxBits = log2Up(nSets) val idxBits = log2Up(nSets)
val untagBits = blockOffBits + idxBits val untagBits = blockOffBits + idxBits
val tagBits = params(PAddrBits) - untagBits val tagBits = p(PAddrBits) - untagBits
val nWays = params(NWays) val nWays = p(NWays)
val wayBits = log2Up(nWays) val wayBits = log2Up(nWays)
val isDM = nWays == 1 val isDM = nWays == 1
val rowBits = params(RowBits) val rowBits = p(RowBits)
val rowBytes = rowBits/8 val rowBytes = rowBits/8
val rowOffBits = log2Up(rowBytes) val rowOffBits = log2Up(rowBytes)
val code = params(ECCCode).getOrElse(new IdentityCode) val code = p(ECCCode).getOrElse(new IdentityCode)
} }
abstract class CacheBundle extends Bundle with CacheParameters abstract class CacheModule(implicit val p: Parameters) extends Module
abstract class CacheModule extends Module with CacheParameters with HasCacheParameters
abstract class CacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasCacheParameters
class StoreGen(typ: UInt, addr: UInt, dat: UInt) { class StoreGen(typ: UInt, addr: UInt, dat: UInt) {
val byte = typ === MT_B || typ === MT_BU val byte = typ === MT_B || typ === MT_BU
@ -66,8 +69,8 @@ class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool) {
val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift) val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
} }
class AMOALU extends CacheModule { class AMOALU(implicit p: Parameters) extends CacheModule()(p) {
val operandBits = params(AmoAluOperandBits) val operandBits = p(AmoAluOperandBits)
require(operandBits == 64) require(operandBits == 64)
val io = new Bundle { val io = new Bundle {
val addr = Bits(INPUT, blockOffBits) val addr = Bits(INPUT, blockOffBits)
@ -125,23 +128,23 @@ class RandomReplacement(ways: Int) extends ReplacementPolicy {
def hit = {} def hit = {}
} }
abstract class Metadata extends CacheBundle { abstract class Metadata(implicit p: Parameters) extends CacheBundle()(p) {
val tag = Bits(width = tagBits) val tag = Bits(width = tagBits)
val coh: CoherenceMetadata val coh: CoherenceMetadata
} }
class MetaReadReq extends CacheBundle { class MetaReadReq(implicit p: Parameters) extends CacheBundle()(p) {
val idx = Bits(width = idxBits) val idx = Bits(width = idxBits)
} }
class MetaWriteReq[T <: Metadata](gen: T) extends MetaReadReq { class MetaWriteReq[T <: Metadata](gen: T)(implicit p: Parameters) extends MetaReadReq()(p) {
val way_en = Bits(width = nWays) val way_en = Bits(width = nWays)
val data = gen.cloneType val data = gen.cloneType
override def cloneType = new MetaWriteReq(gen).asInstanceOf[this.type] override def cloneType = new MetaWriteReq(gen)(p).asInstanceOf[this.type]
} }
class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule { class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) extends CacheModule()(p) {
val rstVal = makeRstVal() val rstVal = onReset()
val io = new Bundle { val io = new Bundle {
val read = Decoupled(new MetaReadReq).flip val read = Decoupled(new MetaReadReq).flip
val write = Decoupled(new MetaWriteReq(rstVal)).flip val write = Decoupled(new MetaWriteReq(rstVal)).flip
@ -166,24 +169,24 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
io.write.ready := !rst io.write.ready := !rst
} }
abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgentParameters { trait HasL2HellaCacheParameters extends HasCacheParameters with HasCoherenceAgentParameters {
val idxMSB = idxBits-1 val idxMSB = idxBits-1
val idxLSB = 0 val idxLSB = 0
val blockAddrBits = params(TLBlockAddrBits) val blockAddrBits = p(TLBlockAddrBits)
val refillCyclesPerBeat = outerDataBits/rowBits val refillCyclesPerBeat = outerDataBits/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats val refillCycles = refillCyclesPerBeat*outerDataBeats
val internalDataBeats = params(CacheBlockBytes)*8/rowBits val internalDataBeats = p(CacheBlockBytes)*8/rowBits
require(refillCyclesPerBeat == 1) require(refillCyclesPerBeat == 1)
val amoAluOperandBits = params(AmoAluOperandBits) val amoAluOperandBits = p(AmoAluOperandBits)
require(amoAluOperandBits <= innerDataBits) require(amoAluOperandBits <= innerDataBits)
require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states
val nSecondaryMisses = params(NSecondaryMisses) val nSecondaryMisses = p(NSecondaryMisses)
val isLastLevelCache = true val isLastLevelCache = true
val ignoresWriteMask = !params(ECCCode).isEmpty val ignoresWriteMask = !p(ECCCode).isEmpty
} }
abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters abstract class L2HellaCacheModule(implicit val p: Parameters) extends Module
abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters { with HasL2HellaCacheParameters {
def doInternalOutputArbitration[T <: Data : ClassTag]( def doInternalOutputArbitration[T <: Data : ClassTag](
out: DecoupledIO[T], out: DecoupledIO[T],
ins: Seq[DecoupledIO[T]]) { ins: Seq[DecoupledIO[T]]) {
@ -192,39 +195,42 @@ abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters {
arb.io.in <> ins arb.io.in <> ins
} }
def doInternalInputRouting[T <: HasL2Id](in: ValidIO[T], outs: Seq[ValidIO[T]]) { def doInternalInputRouting[T <: Bundle with HasL2Id](in: ValidIO[T], outs: Seq[ValidIO[T]]) {
outs.map(_.bits := in.bits) outs.map(_.bits := in.bits)
outs.zipWithIndex.map { case (o,i) => o.valid := in.valid && in.bits.id === UInt(i) } outs.zipWithIndex.map { case (o,i) => o.valid := in.valid && in.bits.id === UInt(i) }
} }
} }
trait HasL2Id extends Bundle with CoherenceAgentParameters { abstract class L2HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasL2HellaCacheParameters
trait HasL2Id extends HasCoherenceAgentParameters {
val id = UInt(width = log2Up(nTransactors + 1)) val id = UInt(width = log2Up(nTransactors + 1))
} }
trait HasL2InternalRequestState extends L2HellaCacheBundle { trait HasL2InternalRequestState extends HasL2HellaCacheParameters {
val tag_match = Bool() val tag_match = Bool()
val meta = new L2Metadata val meta = new L2Metadata
val way_en = Bits(width = nWays) val way_en = Bits(width = nWays)
} }
trait HasL2BeatAddr extends L2HellaCacheBundle { trait HasL2BeatAddr extends HasL2HellaCacheParameters {
val addr_beat = UInt(width = log2Up(refillCycles)) val addr_beat = UInt(width = log2Up(refillCycles))
} }
trait HasL2Data extends L2HellaCacheBundle trait HasL2Data extends HasL2HellaCacheParameters
with HasL2BeatAddr { with HasL2BeatAddr {
val data = UInt(width = rowBits) val data = UInt(width = rowBits)
def hasData(dummy: Int = 0) = Bool(true) def hasData(dummy: Int = 0) = Bool(true)
def hasMultibeatData(dummy: Int = 0) = Bool(refillCycles > 1) def hasMultibeatData(dummy: Int = 0) = Bool(refillCycles > 1)
} }
class L2Metadata extends Metadata with L2HellaCacheParameters { class L2Metadata(implicit p: Parameters) extends Metadata()(p) with HasL2HellaCacheParameters {
val coh = new HierarchicalMetadata val coh = new HierarchicalMetadata
} }
object L2Metadata { object L2Metadata {
def apply(tag: Bits, coh: HierarchicalMetadata) = { def apply(tag: Bits, coh: HierarchicalMetadata)(implicit p: Parameters) = {
val meta = Wire(new L2Metadata) val meta = Wire(new L2Metadata)
meta.tag := tag meta.tag := tag
meta.coh := coh meta.coh := coh
@ -232,31 +238,33 @@ object L2Metadata {
} }
} }
class L2MetaReadReq extends MetaReadReq with HasL2Id { class L2MetaReadReq(implicit p: Parameters) extends MetaReadReq()(p) with HasL2Id {
val tag = Bits(width = tagBits) val tag = Bits(width = tagBits)
} }
class L2MetaWriteReq extends MetaWriteReq[L2Metadata](new L2Metadata) class L2MetaWriteReq(implicit p: Parameters) extends MetaWriteReq[L2Metadata](new L2Metadata)(p)
with HasL2Id { with HasL2Id {
override def cloneType = new L2MetaWriteReq().asInstanceOf[this.type] override def cloneType = new L2MetaWriteReq().asInstanceOf[this.type]
} }
class L2MetaResp extends L2HellaCacheBundle class L2MetaResp(implicit p: Parameters) extends L2HellaCacheBundle()(p)
with HasL2Id with HasL2Id
with HasL2InternalRequestState with HasL2InternalRequestState
trait HasL2MetaReadIO extends L2HellaCacheBundle { trait HasL2MetaReadIO extends HasL2HellaCacheParameters {
val read = Decoupled(new L2MetaReadReq) val read = Decoupled(new L2MetaReadReq)
val resp = Valid(new L2MetaResp).flip val resp = Valid(new L2MetaResp).flip
} }
trait HasL2MetaWriteIO extends L2HellaCacheBundle { trait HasL2MetaWriteIO extends HasL2HellaCacheParameters {
val write = Decoupled(new L2MetaWriteReq) val write = Decoupled(new L2MetaWriteReq)
} }
class L2MetaRWIO extends L2HellaCacheBundle with HasL2MetaReadIO with HasL2MetaWriteIO class L2MetaRWIO(implicit p: Parameters) extends L2HellaCacheBundle()(p)
with HasL2MetaReadIO
with HasL2MetaWriteIO
class L2MetadataArray extends L2HellaCacheModule { class L2MetadataArray(implicit p: Parameters) extends L2HellaCacheModule()(p) {
val io = new L2MetaRWIO().flip val io = new L2MetaRWIO().flip
def onReset = L2Metadata(UInt(0), HierarchicalMetadata.onReset) def onReset = L2Metadata(UInt(0), HierarchicalMetadata.onReset)
@ -274,7 +282,7 @@ class L2MetadataArray extends L2HellaCacheModule {
val s2_tag_match = s2_tag_match_way.orR val s2_tag_match = s2_tag_match_way.orR
val s2_hit_coh = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en))) val s2_hit_coh = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
val replacer = params(Replacer)() val replacer = p(Replacer)()
val s1_replaced_way_en = UIntToOH(replacer.way) val s1_replaced_way_en = UIntToOH(replacer.way)
val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en)) val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) => val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
@ -290,32 +298,36 @@ class L2MetadataArray extends L2HellaCacheModule {
io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
} }
class L2DataReadReq extends L2HellaCacheBundle class L2DataReadReq(implicit p: Parameters) extends L2HellaCacheBundle()(p)
with HasL2BeatAddr with HasL2BeatAddr
with HasL2Id { with HasL2Id {
val addr_idx = UInt(width = idxBits) val addr_idx = UInt(width = idxBits)
val way_en = Bits(width = nWays) val way_en = Bits(width = nWays)
} }
class L2DataWriteReq extends L2DataReadReq class L2DataWriteReq(implicit p: Parameters) extends L2DataReadReq()(p)
with HasL2Data { with HasL2Data {
val wmask = Bits(width = rowBits/8) val wmask = Bits(width = rowBits/8)
} }
class L2DataResp extends L2HellaCacheBundle with HasL2Id with HasL2Data class L2DataResp(implicit p: Parameters) extends L2HellaCacheBundle()(p)
with HasL2Id
with HasL2Data
trait HasL2DataReadIO extends L2HellaCacheBundle { trait HasL2DataReadIO extends HasL2HellaCacheParameters {
val read = Decoupled(new L2DataReadReq) val read = Decoupled(new L2DataReadReq)
val resp = Valid(new L2DataResp).flip val resp = Valid(new L2DataResp).flip
} }
trait HasL2DataWriteIO extends L2HellaCacheBundle { trait HasL2DataWriteIO extends HasL2HellaCacheParameters {
val write = Decoupled(new L2DataWriteReq) val write = Decoupled(new L2DataWriteReq)
} }
class L2DataRWIO extends L2HellaCacheBundle with HasL2DataReadIO with HasL2DataWriteIO class L2DataRWIO(implicit p: Parameters) extends L2HellaCacheBundle()(p)
with HasL2DataReadIO
with HasL2DataWriteIO
class L2DataArray(delay: Int) extends L2HellaCacheModule { class L2DataArray(delay: Int)(implicit p: Parameters) extends L2HellaCacheModule()(p) {
val io = new L2DataRWIO().flip val io = new L2DataRWIO().flip
val array = SeqMem(Vec(Bits(width=8), rowBits/8), nWays*nSets*refillCycles) val array = SeqMem(Vec(Bits(width=8), rowBits/8), nWays*nSets*refillCycles)
@ -333,7 +345,8 @@ class L2DataArray(delay: Int) extends L2HellaCacheModule {
io.write.ready := Bool(true) io.write.ready := Bool(true)
} }
class L2HellaCacheBank extends HierarchicalCoherenceAgent with L2HellaCacheParameters { class L2HellaCacheBank(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p)
with HasL2HellaCacheParameters {
require(isPow2(nSets)) require(isPow2(nSets))
require(isPow2(nWays)) require(isPow2(nWays))
@ -347,12 +360,13 @@ class L2HellaCacheBank extends HierarchicalCoherenceAgent with L2HellaCacheParam
data.io <> tshrfile.io.data data.io <> tshrfile.io.data
} }
class TSHRFileIO extends HierarchicalTLIO { class TSHRFileIO(implicit p: Parameters) extends HierarchicalTLIO()(p) {
val meta = new L2MetaRWIO val meta = new L2MetaRWIO
val data = new L2DataRWIO val data = new L2DataRWIO
} }
class TSHRFile extends L2HellaCacheModule with HasCoherenceAgentWiringHelpers { class TSHRFile(implicit p: Parameters) extends L2HellaCacheModule()(p)
with HasCoherenceAgentWiringHelpers {
val io = new TSHRFileIO val io = new TSHRFileIO
// Create TSHRs for outstanding transactions // Create TSHRs for outstanding transactions
@ -418,15 +432,16 @@ class TSHRFile extends L2HellaCacheModule with HasCoherenceAgentWiringHelpers {
} }
class L2XactTrackerIO extends HierarchicalXactTrackerIO { class L2XactTrackerIO(implicit p: Parameters) extends HierarchicalXactTrackerIO()(p) {
val data = new L2DataRWIO val data = new L2DataRWIO
val meta = new L2MetaRWIO val meta = new L2MetaRWIO
val wb = new L2WritebackIO val wb = new L2WritebackIO
} }
abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters { abstract class L2XactTracker(implicit p: Parameters) extends XactTracker()(p)
with HasL2HellaCacheParameters {
class CacheBlockBuffer { // TODO class CacheBlockBuffer { // TODO
val buffer = Reg(Bits(width = params(CacheBlockBytes)*8)) val buffer = Reg(Bits(width = p(CacheBlockBytes)*8))
def internal = Vec(Bits(width = rowBits), internalDataBeats).fromBits(buffer) def internal = Vec(Bits(width = rowBits), internalDataBeats).fromBits(buffer)
def inner = Vec(Bits(width = innerDataBits), innerDataBeats).fromBits(buffer) def inner = Vec(Bits(width = innerDataBits), innerDataBeats).fromBits(buffer)
@ -440,29 +455,29 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
} else { (UInt(0), inc) } } else { (UInt(0), inc) }
} }
def connectInternalDataBeatCounter[T <: HasL2BeatAddr]( def connectInternalDataBeatCounter[T <: L2HellaCacheBundle with HasL2BeatAddr](
in: DecoupledIO[T], in: DecoupledIO[T],
beat: UInt = UInt(0), beat: UInt = UInt(0),
full_block: Bool = Bool(true)): (UInt, Bool) = { full_block: Bool = Bool(true)): (UInt, Bool) = {
connectDataBeatCounter(in.fire(), in.bits, beat, full_block) connectDataBeatCounter(in.fire(), in.bits, beat, full_block)
} }
def connectInternalDataBeatCounter[T <: HasL2Data]( def connectInternalDataBeatCounter[T <: L2HellaCacheBundle with HasL2Data](
in: ValidIO[T], in: ValidIO[T],
full_block: Bool): Bool = { full_block: Bool): Bool = {
connectDataBeatCounter(in.valid, in.bits, UInt(0), full_block)._2 connectDataBeatCounter(in.valid, in.bits, UInt(0), full_block)._2
} }
def addPendingBitInternal[T <: HasL2BeatAddr](in: DecoupledIO[T]) = def addPendingBitInternal[T <: L2HellaCacheBundle with HasL2BeatAddr](in: DecoupledIO[T]) =
Fill(in.bits.refillCycles, in.fire()) & UIntToOH(in.bits.addr_beat) Fill(in.bits.refillCycles, in.fire()) & UIntToOH(in.bits.addr_beat)
def addPendingBitInternal[T <: HasL2BeatAddr](in: ValidIO[T]) = def addPendingBitInternal[T <: L2HellaCacheBundle with HasL2BeatAddr](in: ValidIO[T]) =
Fill(in.bits.refillCycles, in.valid) & UIntToOH(in.bits.addr_beat) Fill(in.bits.refillCycles, in.valid) & UIntToOH(in.bits.addr_beat)
def dropPendingBit[T <: HasL2BeatAddr] (in: DecoupledIO[T]) = def dropPendingBit[T <: L2HellaCacheBundle with HasL2BeatAddr] (in: DecoupledIO[T]) =
~Fill(in.bits.refillCycles, in.fire()) | ~UIntToOH(in.bits.addr_beat) ~Fill(in.bits.refillCycles, in.fire()) | ~UIntToOH(in.bits.addr_beat)
def dropPendingBitInternal[T <: HasL2BeatAddr] (in: ValidIO[T]) = def dropPendingBitInternal[T <: L2HellaCacheBundle with HasL2BeatAddr] (in: ValidIO[T]) =
~Fill(in.bits.refillCycles, in.valid) | ~UIntToOH(in.bits.addr_beat) ~Fill(in.bits.refillCycles, in.valid) | ~UIntToOH(in.bits.addr_beat)
def addPendingBitWhenBeatHasPartialWritemask(in: DecoupledIO[AcquireFromSrc]): UInt = { def addPendingBitWhenBeatHasPartialWritemask(in: DecoupledIO[AcquireFromSrc]): UInt = {
@ -474,10 +489,10 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
def pinAllReadyValidLow[T <: Data](b: Bundle) { def pinAllReadyValidLow[T <: Data](b: Bundle) {
b.elements.foreach { b.elements.foreach {
_._2 match { _._2 match {
case d: DecoupledIO[T] => case d: DecoupledIO[_] =>
if(d.ready.dir == OUTPUT) d.ready := Bool(false) if(d.ready.dir == OUTPUT) d.ready := Bool(false)
else if(d.valid.dir == OUTPUT) d.valid := Bool(false) else if(d.valid.dir == OUTPUT) d.valid := Bool(false)
case v: ValidIO[T] => if(v.valid.dir == OUTPUT) v.valid := Bool(false) case v: ValidIO[_] => if(v.valid.dir == OUTPUT) v.valid := Bool(false)
case b: Bundle => pinAllReadyValidLow(b) case b: Bundle => pinAllReadyValidLow(b)
case _ => case _ =>
} }
@ -485,14 +500,14 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
} }
} }
class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker { class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTracker()(p) {
val io = new L2XactTrackerIO val io = new L2XactTrackerIO
pinAllReadyValidLow(io) pinAllReadyValidLow(io)
val s_idle :: s_meta_read :: s_meta_resp :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 5) val s_idle :: s_meta_read :: s_meta_resp :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 5)
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 })) val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => p(InnerTLId); case TLDataBits => 0 }))
val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits))) val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
val xact_way_en = Reg{ Bits(width = nWays) } val xact_way_en = Reg{ Bits(width = nWays) }
val xact_old_meta = Reg{ new L2Metadata } val xact_old_meta = Reg{ new L2Metadata }
@ -579,7 +594,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
} }
class L2AcquireTracker(trackerId: Int) extends L2XactTracker { class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTracker()(p) {
val io = new L2XactTrackerIO val io = new L2XactTrackerIO
pinAllReadyValidLow(io) pinAllReadyValidLow(io)
@ -587,7 +602,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
// State holding transaction metadata // State holding transaction metadata
val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) })) val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => p(InnerTLId) }))
val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits))) val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8))) val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8)))
val xact_tag_match = Reg{ Bool() } val xact_tag_match = Reg{ Bool() }
@ -667,15 +682,15 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
wmask_buffer(beat) := ~UInt(0, wmask_buffer.head.getWidth) wmask_buffer(beat) := ~UInt(0, wmask_buffer.head.getWidth)
when(xact.is(Acquire.putAtomicType) && xact.addr_beat === beat) { amo_result := old_data } when(xact.is(Acquire.putAtomicType) && xact.addr_beat === beat) { amo_result := old_data }
} }
def mergeDataInternal[T <: HasL2Data with HasL2BeatAddr](in: ValidIO[T]) { def mergeDataInternal[T <: L2HellaCacheBundle with HasL2Data with HasL2BeatAddr](in: ValidIO[T]) {
when(in.valid) { mergeData(rowBits)(in.bits.addr_beat, in.bits.data) } when(in.valid) { mergeData(rowBits)(in.bits.addr_beat, in.bits.data) }
} }
def mergeDataInner[T <: HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[T]) { def mergeDataInner[T <: TLBundle with HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[T]) {
when(in.fire() && in.bits.hasData()) { when(in.fire() && in.bits.hasData()) {
mergeData(innerDataBits)(in.bits.addr_beat, in.bits.data) mergeData(innerDataBits)(in.bits.addr_beat, in.bits.data)
} }
} }
def mergeDataOuter[T <: HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[T]) { def mergeDataOuter[T <: TLBundle with HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[T]) {
when(in.fire() && in.bits.hasData()) { when(in.fire() && in.bits.hasData()) {
mergeData(outerDataBits)(in.bits.addr_beat, in.bits.data) mergeData(outerDataBits)(in.bits.addr_beat, in.bits.data)
} }
@ -956,24 +971,24 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
"AcquireTracker accepted data beat from different network source than initial request.") "AcquireTracker accepted data beat from different network source than initial request.")
} }
class L2WritebackReq extends L2Metadata with HasL2Id { class L2WritebackReq(implicit p: Parameters) extends L2Metadata()(p) with HasL2Id {
val idx = Bits(width = idxBits) val idx = Bits(width = idxBits)
val way_en = Bits(width = nWays) val way_en = Bits(width = nWays)
} }
class L2WritebackResp extends L2HellaCacheBundle with HasL2Id class L2WritebackResp(implicit p: Parameters) extends L2HellaCacheBundle()(p) with HasL2Id
class L2WritebackIO extends L2HellaCacheBundle { class L2WritebackIO(implicit p: Parameters) extends L2HellaCacheBundle()(p) {
val req = Decoupled(new L2WritebackReq) val req = Decoupled(new L2WritebackReq)
val resp = Valid(new L2WritebackResp).flip val resp = Valid(new L2WritebackResp).flip
} }
class L2WritebackUnitIO extends HierarchicalXactTrackerIO { class L2WritebackUnitIO(implicit p: Parameters) extends HierarchicalXactTrackerIO()(p) {
val wb = new L2WritebackIO().flip val wb = new L2WritebackIO().flip
val data = new L2DataRWIO val data = new L2DataRWIO
} }
class L2WritebackUnit(trackerId: Int) extends L2XactTracker { class L2WritebackUnit(trackerId: Int)(implicit p: Parameters) extends L2XactTracker()(p) {
val io = new L2WritebackUnitIO val io = new L2WritebackUnitIO
pinAllReadyValidLow(io) pinAllReadyValidLow(io)

82
uncore/src/main/scala/coherence.scala
View File

@ -8,10 +8,10 @@ import Chisel._
* HasClientSideCoherencePolicy, for client coherence agents * HasClientSideCoherencePolicy, for client coherence agents
* HasManagerSideCoherencePolicy, for manager coherence agents * HasManagerSideCoherencePolicy, for manager coherence agents
*/ */
abstract class CoherencePolicy(val dir: DirectoryRepresentation) extends abstract class CoherencePolicy(val dir: DirectoryRepresentation)
HasCustomTileLinkMessageTypes with extends HasCustomTileLinkMessageTypes
HasClientSideCoherencePolicy with with HasClientSideCoherencePolicy
HasManagerSideCoherencePolicy with HasManagerSideCoherencePolicy
/** This API defines the custom, coherence-policy-defined message types, /** This API defines the custom, coherence-policy-defined message types,
* as opposed to the built-in ones found in tilelink.scala. * as opposed to the built-in ones found in tilelink.scala.
@ -73,7 +73,6 @@ trait HasClientSideCoherencePolicy {
def getReleaseType(p: Probe, meta: ClientMetadata): UInt def getReleaseType(p: Probe, meta: ClientMetadata): UInt
// Mutate ClientMetadata based on messages or cmds // Mutate ClientMetadata based on messages or cmds
def clientMetadataOnReset: ClientMetadata
def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata): ClientMetadata def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata): ClientMetadata
def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata): ClientMetadata def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata): ClientMetadata
def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata): ClientMetadata def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata): ClientMetadata
@ -101,12 +100,11 @@ trait HasManagerSideCoherencePolicy extends HasDirectoryRepresentation {
def getExclusiveGrantType(): UInt def getExclusiveGrantType(): UInt
// Mutate ManagerMetadata based on messages or cmds // Mutate ManagerMetadata based on messages or cmds
def managerMetadataOnReset: ManagerMetadata
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata): ManagerMetadata def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata): ManagerMetadata
def managerMetadataOnGrant(outgoing: Grant, dst: UInt, meta: ManagerMetadata) = def managerMetadataOnGrant(outgoing: Grant, dst: UInt, meta: ManagerMetadata) =
ManagerMetadata(sharers=Mux(outgoing.isBuiltInType(), // Assumes all built-ins are uncached ManagerMetadata(sharers=Mux(outgoing.isBuiltInType(), // Assumes all built-ins are uncached
meta.sharers, meta.sharers,
dir.push(meta.sharers, dst))) dir.push(meta.sharers, dst)))(meta.p)
//state = meta.state) TODO: Fix 0-width wires in Chisel //state = meta.state) TODO: Fix 0-width wires in Chisel
} }
@ -158,19 +156,17 @@ class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
probeInvalidate -> getReleaseType(M_FLUSH, meta), probeInvalidate -> getReleaseType(M_FLUSH, meta),
probeCopy -> getReleaseType(M_CLEAN, meta))) probeCopy -> getReleaseType(M_CLEAN, meta)))
def clientMetadataOnReset = ClientMetadata(clientInvalid)
def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) = meta def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) = meta
def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) = def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) =
ClientMetadata(Mux(cmd === M_FLUSH, clientInvalid, meta.state)) ClientMetadata(Mux(cmd === M_FLUSH, clientInvalid, meta.state))(meta.p)
def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) = def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) =
ClientMetadata(Mux(incoming.isBuiltInType(), clientInvalid, clientValid)) ClientMetadata(Mux(incoming.isBuiltInType(), clientInvalid, clientValid))(meta.p)
def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) = def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) =
ClientMetadata(Mux(incoming.p_type === probeInvalidate, ClientMetadata(Mux(incoming.p_type === probeInvalidate,
clientInvalid, meta.state)) clientInvalid, meta.state))(meta.p)
// Manager states and functions: // Manager states and functions:
val nManagerStates = 0 // We don't actually need any states for this protocol val nManagerStates = 0 // We don't actually need any states for this protocol
@ -196,10 +192,8 @@ class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
def getGrantType(a: Acquire, meta: ManagerMetadata): UInt = grantExclusive def getGrantType(a: Acquire, meta: ManagerMetadata): UInt = grantExclusive
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnReset = ManagerMetadata()
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src)) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,
incoming.is(releaseInvalidateAck) -> popped)) incoming.is(releaseInvalidateAck) -> popped))
@ -252,28 +246,26 @@ class MEICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
probeDowngrade -> getReleaseType(M_PRODUCE, meta), probeDowngrade -> getReleaseType(M_PRODUCE, meta),
probeCopy -> getReleaseType(M_CLEAN, meta))) probeCopy -> getReleaseType(M_CLEAN, meta)))
def clientMetadataOnReset = ClientMetadata(clientInvalid)
def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) = def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) =
ClientMetadata(Mux(isWrite(cmd), clientExclusiveDirty, meta.state)) ClientMetadata(Mux(isWrite(cmd), clientExclusiveDirty, meta.state))(meta.p)
def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) = def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
MuxLookup(cmd, meta.state, Array( MuxLookup(cmd, meta.state, Array(
M_FLUSH -> clientInvalid, M_FLUSH -> clientInvalid,
M_CLEAN -> Mux(meta.state === clientExclusiveDirty, clientExclusiveClean, meta.state)))) M_CLEAN -> Mux(meta.state === clientExclusiveDirty, clientExclusiveClean, meta.state))))(meta.p)
def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) = def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
Mux(incoming.isBuiltInType(), clientInvalid, Mux(incoming.isBuiltInType(), clientInvalid,
Mux(isWrite(cmd), clientExclusiveDirty, clientExclusiveClean))) Mux(isWrite(cmd), clientExclusiveDirty, clientExclusiveClean)))(meta.p)
def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) = def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
MuxLookup(incoming.p_type, meta.state, Array( MuxLookup(incoming.p_type, meta.state, Array(
probeInvalidate -> clientInvalid, probeInvalidate -> clientInvalid,
probeDowngrade -> clientExclusiveClean, probeDowngrade -> clientExclusiveClean,
probeCopy -> meta.state))) probeCopy -> meta.state)))(meta.p)
// Manager states and functions: // Manager states and functions:
val nManagerStates = 0 // We don't actually need any states for this protocol val nManagerStates = 0 // We don't actually need any states for this protocol
@ -299,10 +291,8 @@ class MEICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
def getGrantType(a: Acquire, meta: ManagerMetadata): UInt = grantExclusive def getGrantType(a: Acquire, meta: ManagerMetadata): UInt = grantExclusive
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnReset = ManagerMetadata()
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src)) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,
incoming.is(releaseInvalidateAck) -> popped)) incoming.is(releaseInvalidateAck) -> popped))
@ -355,17 +345,15 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
probeDowngrade -> getReleaseType(M_PRODUCE, meta), probeDowngrade -> getReleaseType(M_PRODUCE, meta),
probeCopy -> getReleaseType(M_CLEAN, meta))) probeCopy -> getReleaseType(M_CLEAN, meta)))
def clientMetadataOnReset = ClientMetadata(clientInvalid)
def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) = def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) =
ClientMetadata(Mux(isWrite(cmd), clientExclusiveDirty, meta.state)) ClientMetadata(Mux(isWrite(cmd), clientExclusiveDirty, meta.state))(meta.p)
def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) = def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
MuxLookup(cmd, meta.state, Array( MuxLookup(cmd, meta.state, Array(
M_FLUSH -> clientInvalid, M_FLUSH -> clientInvalid,
M_PRODUCE -> Mux(clientStatesWithWritePermission.contains(meta.state), M_PRODUCE -> Mux(clientStatesWithWritePermission.contains(meta.state),
clientShared, meta.state)))) clientShared, meta.state))))(meta.p)
def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) = def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
@ -373,14 +361,14 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
MuxLookup(incoming.g_type, clientInvalid, Array( MuxLookup(incoming.g_type, clientInvalid, Array(
grantShared -> clientShared, grantShared -> clientShared,
grantExclusive -> clientExclusiveDirty, grantExclusive -> clientExclusiveDirty,
grantExclusiveAck -> clientExclusiveDirty)))) grantExclusiveAck -> clientExclusiveDirty))))(meta.p)
def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) = def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
MuxLookup(incoming.p_type, meta.state, Array( MuxLookup(incoming.p_type, meta.state, Array(
probeInvalidate -> clientInvalid, probeInvalidate -> clientInvalid,
probeDowngrade -> clientShared, probeDowngrade -> clientShared,
probeCopy -> meta.state))) probeCopy -> meta.state)))(meta.p)
// Manager states and functions: // Manager states and functions:
val nManagerStates = 0 // TODO: We could add a Shared state to avoid probing val nManagerStates = 0 // TODO: We could add a Shared state to avoid probing
@ -418,10 +406,8 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
grantExclusive) grantExclusive)
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnReset = ManagerMetadata()
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src)) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,
incoming.is(releaseInvalidateAck) -> popped)) incoming.is(releaseInvalidateAck) -> popped))
@ -474,10 +460,8 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
probeDowngrade -> getReleaseType(M_PRODUCE, meta), probeDowngrade -> getReleaseType(M_PRODUCE, meta),
probeCopy -> getReleaseType(M_CLEAN, meta))) probeCopy -> getReleaseType(M_CLEAN, meta)))
def clientMetadataOnReset = ClientMetadata(clientInvalid)
def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) = def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) =
ClientMetadata(Mux(isWrite(cmd), clientExclusiveDirty, meta.state)) ClientMetadata(Mux(isWrite(cmd), clientExclusiveDirty, meta.state))(meta.p)
def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) = def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
@ -485,7 +469,8 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
M_FLUSH -> clientInvalid, M_FLUSH -> clientInvalid,
M_PRODUCE -> Mux(clientStatesWithWritePermission.contains(meta.state), M_PRODUCE -> Mux(clientStatesWithWritePermission.contains(meta.state),
clientShared, meta.state), clientShared, meta.state),
M_CLEAN -> Mux(meta.state === clientExclusiveDirty, clientExclusiveClean, meta.state)))) M_CLEAN -> Mux(meta.state === clientExclusiveDirty,
clientExclusiveClean, meta.state))))(meta.p)
def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) = def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
@ -493,14 +478,14 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
MuxLookup(incoming.g_type, clientInvalid, Array( MuxLookup(incoming.g_type, clientInvalid, Array(
grantShared -> clientShared, grantShared -> clientShared,
grantExclusive -> Mux(isWrite(cmd), clientExclusiveDirty, clientExclusiveClean), grantExclusive -> Mux(isWrite(cmd), clientExclusiveDirty, clientExclusiveClean),
grantExclusiveAck -> clientExclusiveDirty)))) grantExclusiveAck -> clientExclusiveDirty))))(meta.p)
def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) = def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
MuxLookup(incoming.p_type, meta.state, Array( MuxLookup(incoming.p_type, meta.state, Array(
probeInvalidate -> clientInvalid, probeInvalidate -> clientInvalid,
probeDowngrade -> clientShared, probeDowngrade -> clientShared,
probeCopy -> meta.state))) probeCopy -> meta.state)))(meta.p)
// Manager states and functions: // Manager states and functions:
val nManagerStates = 0 // TODO: We could add a Shared state to avoid probing val nManagerStates = 0 // TODO: We could add a Shared state to avoid probing
@ -538,10 +523,8 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
grantExclusive) grantExclusive)
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnReset = ManagerMetadata()
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src)) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,
incoming.is(releaseInvalidateAck) -> popped)) incoming.is(releaseInvalidateAck) -> popped))
@ -605,14 +588,12 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
Mux(dirty, with_data, without_data) Mux(dirty, with_data, without_data)
} }
def clientMetadataOnReset = ClientMetadata(clientInvalid)
def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) = def clientMetadataOnHit(cmd: UInt, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
Mux(isWrite(cmd), MuxLookup(meta.state, clientExclusiveDirty, Array( Mux(isWrite(cmd), MuxLookup(meta.state, clientExclusiveDirty, Array(
clientExclusiveClean -> clientExclusiveDirty, clientExclusiveClean -> clientExclusiveDirty,
clientMigratoryClean -> clientMigratoryDirty)), clientMigratoryClean -> clientMigratoryDirty)),
meta.state)) meta.state))(meta.p)
def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) = def clientMetadataOnCacheControl(cmd: UInt, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
@ -622,7 +603,7 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
clientShared, meta.state), clientShared, meta.state),
M_CLEAN -> MuxLookup(meta.state, meta.state, Array( M_CLEAN -> MuxLookup(meta.state, meta.state, Array(
clientExclusiveDirty -> clientExclusiveClean, clientExclusiveDirty -> clientExclusiveClean,
clientMigratoryDirty -> clientMigratoryClean))))) clientMigratoryDirty -> clientMigratoryClean)))))(meta.p)
def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) = def clientMetadataOnGrant(incoming: Grant, cmd: UInt, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
@ -631,7 +612,8 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
grantShared -> clientShared, grantShared -> clientShared,
grantExclusive -> Mux(isWrite(cmd), clientExclusiveDirty, clientExclusiveClean), grantExclusive -> Mux(isWrite(cmd), clientExclusiveDirty, clientExclusiveClean),
grantExclusiveAck -> clientExclusiveDirty, grantExclusiveAck -> clientExclusiveDirty,
grantReadMigratory -> Mux(isWrite(cmd), clientMigratoryDirty, clientMigratoryClean))))) grantReadMigratory -> Mux(isWrite(cmd),
clientMigratoryDirty, clientMigratoryClean)))))(meta.p)
def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) = def clientMetadataOnProbe(incoming: Probe, meta: ClientMetadata) =
ClientMetadata( ClientMetadata(
@ -644,7 +626,7 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
clientExclusiveDirty -> clientSharedByTwo, clientExclusiveDirty -> clientSharedByTwo,
clientSharedByTwo -> clientShared, clientSharedByTwo -> clientShared,
clientMigratoryClean -> clientSharedByTwo, clientMigratoryClean -> clientSharedByTwo,
clientMigratoryDirty -> clientInvalid))))) clientMigratoryDirty -> clientInvalid)))))(meta.p)
// Manager states and functions: // Manager states and functions:
val nManagerStates = 0 // TODO: we could add some states to reduce the number of message types val nManagerStates = 0 // TODO: we could add some states to reduce the number of message types
@ -681,10 +663,8 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
acquireInvalidateOthers -> grantExclusiveAck)) //TODO: add this to MESI for broadcast? acquireInvalidateOthers -> grantExclusiveAck)) //TODO: add this to MESI for broadcast?
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnReset = ManagerMetadata()
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src)) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,
incoming.is(releaseInvalidateAck) -> popped, incoming.is(releaseInvalidateAck) -> popped,

101
uncore/src/main/scala/htif.scala
View File

@ -4,57 +4,58 @@ package uncore
import Chisel._ import Chisel._
import Chisel.ImplicitConversions._ import Chisel.ImplicitConversions._
import junctions.SMIIO import junctions._
case object HTIFWidth extends Field[Int] case object HtifKey extends Field[HtifParameters]
case object HTIFNSCR extends Field[Int]
case object HTIFOffsetBits extends Field[Int]
case object HTIFNCores extends Field[Int]
case object HTIFSCRDataBits extends Field[Int]
abstract trait HTIFParameters extends UsesParameters { case class HtifParameters(width: Int, nCores: Int, offsetBits: Int, nSCR: Int = 64)
val dataBits = params(TLDataBits)
val dataBeats = params(TLDataBeats) trait HasHtifParameters {
val w = params(HTIFWidth) implicit val p: Parameters
val nSCR = params(HTIFNSCR) lazy val external = p(HtifKey)
val scrAddrBits = log2Up(nSCR) lazy val dataBits = p(TLDataBits)
val scrDataBits = params(HTIFSCRDataBits) lazy val dataBeats = p(TLDataBeats)
val scrDataBytes = scrDataBits / 8 lazy val w = external.width
val offsetBits = params(HTIFOffsetBits) lazy val nSCR = external.nSCR
val nCores = params(HTIFNCores) lazy val scrAddrBits = log2Up(nSCR)
lazy val scrDataBits = 64
lazy val scrDataBytes = scrDataBits / 8
lazy val offsetBits = external.offsetBits
lazy val nCores = external.nCores
} }
abstract class HTIFBundle extends Bundle with HTIFParameters abstract class HtifModule(implicit val p: Parameters) extends Module with HasHtifParameters
abstract class HtifBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasHtifParameters
class HostIO extends HTIFBundle class HostIO(implicit p: Parameters) extends HtifBundle()(p) {
{
val clk = Bool(OUTPUT) val clk = Bool(OUTPUT)
val clk_edge = Bool(OUTPUT) val clk_edge = Bool(OUTPUT)
val in = Decoupled(Bits(width = w)).flip val in = Decoupled(Bits(width = w)).flip
val out = Decoupled(Bits(width = w)) val out = Decoupled(Bits(width = w))
val debug_stats_pcr = Bool(OUTPUT) val debug_stats_csr = Bool(OUTPUT)
} }
class HTIFIO extends HTIFBundle { class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
val reset = Bool(INPUT) val reset = Bool(INPUT)
val id = UInt(INPUT, log2Up(nCores)) val id = UInt(INPUT, log2Up(nCores))
val pcr = new SMIIO(scrDataBits, 12).flip val csr = new SMIIO(scrDataBits, 12).flip
val ipi_req = Decoupled(Bits(width = log2Up(nCores))) val ipi_req = Decoupled(Bits(width = log2Up(nCores)))
val ipi_rep = Decoupled(Bool()).flip val ipi_rep = Decoupled(Bool()).flip
val debug_stats_pcr = Bool(OUTPUT) val debug_stats_csr = Bool(OUTPUT)
// wired directly to stats register // wired directly to stats register
// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work // expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
} }
class HTIF(pcr_RESET: Int) extends Module with HTIFParameters { class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHtifParameters {
val io = new Bundle { val io = new Bundle {
val host = new HostIO val host = new HostIO
val cpu = Vec(new HTIFIO, nCores).flip val cpu = Vec(new HtifIO, nCores).flip
val mem = new ClientUncachedTileLinkIO val mem = new ClientUncachedTileLinkIO
val scr = new SMIIO(scrDataBits, scrAddrBits) val scr = new SMIIO(scrDataBits, scrAddrBits)
} }
io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_) io.host.debug_stats_csr := io.cpu.map(_.debug_stats_csr).reduce(_||_)
// system is 'interesting' if any tile is 'interesting' // system is 'interesting' if any tile is 'interesting'
val short_request_bits = 64 val short_request_bits = 64
@ -93,9 +94,9 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(UInt(), 6) val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(UInt(), 6)
val pcr_addr = addr(io.cpu(0).pcr.req.bits.addr.getWidth-1, 0) val csr_addr = addr(io.cpu(0).csr.req.bits.addr.getWidth-1, 0)
val pcr_coreid = addr(log2Up(nCores)-1+20+1,20) val csr_coreid = addr(log2Up(nCores)-1+20+1,20)
val pcr_wdata = packet_ram(0) val csr_wdata = packet_ram(0)
val bad_mem_packet = size(offsetBits-1-3,0).orR || addr(offsetBits-1-3,0).orR val bad_mem_packet = size(offsetBits-1-3,0).orR || addr(offsetBits-1-3,0).orR
val nack = Mux(cmd === cmd_readmem || cmd === cmd_writemem, bad_mem_packet, val nack = Mux(cmd === cmd_readmem || cmd === cmd_writemem, bad_mem_packet,
@ -114,7 +115,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr || cmd === cmd_writecr), size, UInt(0)) val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr || cmd === cmd_writecr), size, UInt(0))
val tx_done = io.host.out.ready && tx_subword_count.andR && (tx_word_count === tx_size || tx_word_count > UInt(0) && packet_ram_raddr.andR) val tx_done = io.host.out.ready && tx_subword_count.andR && (tx_word_count === tx_size || tx_word_count > UInt(0) && packet_ram_raddr.andR)
val state_rx :: state_pcr_req :: state_pcr_resp :: state_mem_rreq :: state_mem_wreq :: state_mem_rresp :: state_mem_wresp :: state_tx :: Nil = Enum(UInt(), 8) val state_rx :: state_csr_req :: state_csr_resp :: state_mem_rreq :: state_mem_wreq :: state_mem_rresp :: state_mem_wresp :: state_tx :: Nil = Enum(UInt(), 8)
val state = Reg(init=state_rx) val state = Reg(init=state_rx)
val (cnt, cnt_done) = Counter((state === state_mem_wreq && io.mem.acquire.ready) || val (cnt, cnt_done) = Counter((state === state_mem_wreq && io.mem.acquire.ready) ||
@ -123,7 +124,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
when (state === state_rx && rx_done) { when (state === state_rx && rx_done) {
state := Mux(rx_cmd === cmd_readmem, state_mem_rreq, state := Mux(rx_cmd === cmd_readmem, state_mem_rreq,
Mux(rx_cmd === cmd_writemem, state_mem_wreq, Mux(rx_cmd === cmd_writemem, state_mem_wreq,
Mux(rx_cmd === cmd_readcr || rx_cmd === cmd_writecr, state_pcr_req, Mux(rx_cmd === cmd_readcr || rx_cmd === cmd_writecr, state_csr_req,
state_tx))) state_tx)))
} }
when (state === state_mem_wreq) { when (state === state_mem_wreq) {
@ -171,17 +172,17 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
GetBlock(addr_block = init_addr)) GetBlock(addr_block = init_addr))
io.mem.grant.ready := Bool(true) io.mem.grant.ready := Bool(true)
val pcrReadData = Reg(Bits(width = io.cpu(0).pcr.resp.bits.getWidth)) val csrReadData = Reg(Bits(width = io.cpu(0).csr.resp.bits.getWidth))
for (i <- 0 until nCores) { for (i <- 0 until nCores) {
val my_reset = Reg(init=Bool(true)) val my_reset = Reg(init=Bool(true))
val my_ipi = Reg(init=Bool(false)) val my_ipi = Reg(init=Bool(false))
val cpu = io.cpu(i) val cpu = io.cpu(i)
val me = pcr_coreid === UInt(i) val me = csr_coreid === UInt(i)
cpu.pcr.req.valid := state === state_pcr_req && me && pcr_addr != UInt(pcr_RESET) cpu.csr.req.valid := state === state_csr_req && me && csr_addr != UInt(csr_RESET)
cpu.pcr.req.bits.rw := cmd === cmd_writecr cpu.csr.req.bits.rw := cmd === cmd_writecr
cpu.pcr.req.bits.addr := pcr_addr cpu.csr.req.bits.addr := csr_addr
cpu.pcr.req.bits.data := pcr_wdata cpu.csr.req.bits.data := csr_wdata
cpu.reset := my_reset cpu.reset := my_reset
when (cpu.ipi_rep.ready) { when (cpu.ipi_rep.ready) {
@ -195,32 +196,32 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
} }
} }
when (cpu.pcr.req.fire()) { state := state_pcr_resp } when (cpu.csr.req.fire()) { state := state_csr_resp }
when (state === state_pcr_req && me && pcr_addr === UInt(pcr_RESET)) { when (state === state_csr_req && me && csr_addr === UInt(csr_RESET)) {
when (cmd === cmd_writecr) { when (cmd === cmd_writecr) {
my_reset := pcr_wdata(0) my_reset := csr_wdata(0)
} }
pcrReadData := my_reset.toBits csrReadData := my_reset.toBits
state := state_tx state := state_tx
} }
cpu.pcr.resp.ready := Bool(true) cpu.csr.resp.ready := Bool(true)
when (state === state_pcr_resp && cpu.pcr.resp.valid) { when (state === state_csr_resp && cpu.csr.resp.valid) {
pcrReadData := cpu.pcr.resp.bits csrReadData := cpu.csr.resp.bits
state := state_tx state := state_tx
} }
} }
io.scr.req.valid := (state === state_pcr_req && pcr_coreid.andR) io.scr.req.valid := (state === state_csr_req && csr_coreid.andR)
io.scr.req.bits.addr := addr(scrAddrBits - 1, 0).toUInt io.scr.req.bits.addr := addr(scrAddrBits - 1, 0).toUInt
io.scr.req.bits.data := pcr_wdata io.scr.req.bits.data := csr_wdata
io.scr.req.bits.rw := (cmd === cmd_writecr) io.scr.req.bits.rw := (cmd === cmd_writecr)
io.scr.resp.ready := Bool(true) io.scr.resp.ready := Bool(true)
when (io.scr.req.fire()) { state := state_pcr_resp } when (io.scr.req.fire()) { state := state_csr_resp }
when (state === state_pcr_resp && io.scr.resp.valid) { when (state === state_csr_resp && io.scr.resp.valid) {
pcrReadData := io.scr.resp.bits csrReadData := io.scr.resp.bits
state := state_tx state := state_tx
} }
@ -228,7 +229,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd) val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd)
val tx_header = Cat(addr, seqno, tx_size, tx_cmd_ext) val tx_header = Cat(addr, seqno, tx_size, tx_cmd_ext)
val tx_data = Mux(tx_word_count === UInt(0), tx_header, val tx_data = Mux(tx_word_count === UInt(0), tx_header,
Mux(cmd === cmd_readcr || cmd === cmd_writecr, pcrReadData, Mux(cmd === cmd_readcr || cmd === cmd_writecr, csrReadData,
packet_ram(packet_ram_raddr))) packet_ram(packet_ram_raddr)))
io.host.in.ready := state === state_rx io.host.in.ready := state === state_rx

58
uncore/src/main/scala/metadata.scala
View File

@ -4,9 +4,8 @@ package uncore
import Chisel._ import Chisel._
/** Base class to represent coherence information in clients and managers */ /** Base class to represent coherence information in clients and managers */
abstract class CoherenceMetadata extends Bundle { abstract class CoherenceMetadata(implicit p: Parameters) extends TLBundle()(p) {
val co = params(TLCoherencePolicy) val co = tlCoh
val id = params(TLId)
} }
/** Stores the client-side coherence information, /** Stores the client-side coherence information,
@ -14,7 +13,7 @@ abstract class CoherenceMetadata extends Bundle {
* Its API can be used to make TileLink messages in response to * Its API can be used to make TileLink messages in response to
* memory operations or [[uncore.Probe]] messages. * memory operations or [[uncore.Probe]] messages.
*/ */
class ClientMetadata extends CoherenceMetadata { class ClientMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
/** Actual state information stored in this bundle */ /** Actual state information stored in this bundle */
val state = UInt(width = co.clientStateWidth) val state = UInt(width = co.clientStateWidth)
@ -53,8 +52,7 @@ class ClientMetadata extends CoherenceMetadata {
a_type = co.getAcquireType(op_code, this), a_type = co.getAcquireType(op_code, this),
client_xact_id = client_xact_id, client_xact_id = client_xact_id,
addr_block = addr_block, addr_block = addr_block,
union = Cat(op_code, Bool(true))), union = Cat(op_code, Bool(true)))(p))
{ case TLId => id })
} }
/** Constructs a Release message based on this metadata on cache control op /** Constructs a Release message based on this metadata on cache control op
@ -76,7 +74,7 @@ class ClientMetadata extends CoherenceMetadata {
client_xact_id = client_xact_id, client_xact_id = client_xact_id,
addr_block = addr_block, addr_block = addr_block,
addr_beat = addr_beat, addr_beat = addr_beat,
data = data), { case TLId => id }) data = data)(p))
} }
/** Constructs a Release message based on this metadata on an eviction /** Constructs a Release message based on this metadata on an eviction
@ -114,7 +112,7 @@ class ClientMetadata extends CoherenceMetadata {
client_xact_id = UInt(0), client_xact_id = UInt(0),
addr_block = prb.addr_block, addr_block = prb.addr_block,
addr_beat = addr_beat, addr_beat = addr_beat,
data = data), { case TLId => id }) data = data)(p))
} }
/** New metadata after receiving a [[uncore.Grant]] /** New metadata after receiving a [[uncore.Grant]]
@ -123,38 +121,38 @@ class ClientMetadata extends CoherenceMetadata {
* @param pending the mem op that triggered this transaction * @param pending the mem op that triggered this transaction
*/ */
def onGrant(incoming: Grant, pending: UInt): ClientMetadata = def onGrant(incoming: Grant, pending: UInt): ClientMetadata =
Bundle(co.clientMetadataOnGrant(incoming, pending, this), { case TLId => id }) co.clientMetadataOnGrant(incoming, pending, this)
/** New metadata after receiving a [[uncore.Probe]] /** New metadata after receiving a [[uncore.Probe]]
* *
* @param incoming the incoming [[uncore.Probe]] * @param incoming the incoming [[uncore.Probe]]
*/ */
def onProbe(incoming: Probe): ClientMetadata = def onProbe(incoming: Probe): ClientMetadata =
Bundle(co.clientMetadataOnProbe(incoming, this), { case TLId => id }) co.clientMetadataOnProbe(incoming, this)
/** New metadata after a op_code hits this block /** New metadata after a op_code hits this block
* *
* @param op_code a memory operation from [[uncore.constants.MemoryOpConstants]] * @param op_code a memory operation from [[uncore.constants.MemoryOpConstants]]
*/ */
def onHit(op_code: UInt): ClientMetadata = def onHit(op_code: UInt): ClientMetadata =
Bundle(co.clientMetadataOnHit(op_code, this), { case TLId => id }) co.clientMetadataOnHit(op_code, this)
/** New metadata after op_code releases permissions on this block /** New metadata after op_code releases permissions on this block
* *
* @param op_code a memory operation from [[uncore.constants.MemoryOpConstants]] * @param op_code a memory operation from [[uncore.constants.MemoryOpConstants]]
*/ */
def onCacheControl(op_code: UInt): ClientMetadata = def onCacheControl(op_code: UInt): ClientMetadata =
Bundle(co.clientMetadataOnCacheControl(op_code, this), { case TLId => id }) co.clientMetadataOnCacheControl(op_code, this)
} }
/** Factories for ClientMetadata, including on reset */ /** Factories for ClientMetadata, including on reset */
object ClientMetadata { object ClientMetadata {
def apply(state: UInt) = { def apply(state: UInt)(implicit p: Parameters) = {
val meta = Wire(new ClientMetadata) val meta = Wire(new ClientMetadata)
meta.state := state meta.state := state
meta meta
} }
def onReset = new ClientMetadata().co.clientMetadataOnReset def onReset(implicit p: Parameters) = ClientMetadata(UInt(0))(p) // TODO: assumes clientInvalid === 0
} }
/** Stores manager-side information about the status /** Stores manager-side information about the status
@ -162,7 +160,7 @@ object ClientMetadata {
* *
* Its API can be used to create [[uncore.Probe]] and [[uncore.Grant]] messages. * Its API can be used to create [[uncore.Probe]] and [[uncore.Grant]] messages.
*/ */
class ManagerMetadata extends CoherenceMetadata { class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
// Currently no coherence policies assume manager-side state information // Currently no coherence policies assume manager-side state information
// val state = UInt(width = co.masterStateWidth) TODO: Fix 0-width wires in Chisel // val state = UInt(width = co.masterStateWidth) TODO: Fix 0-width wires in Chisel
@ -191,7 +189,7 @@ class ManagerMetadata extends CoherenceMetadata {
* @param acq Acquire message triggering this Probe * @param acq Acquire message triggering this Probe
*/ */
def makeProbe(dst: UInt, acq: Acquire): ProbeToDst = def makeProbe(dst: UInt, acq: Acquire): ProbeToDst =
Bundle(Probe(dst, co.getProbeType(acq, this), acq.addr_block), { case TLId => id }) Bundle(Probe(dst, co.getProbeType(acq, this), acq.addr_block)(p))
/** Construct an appropriate [[uncore.ProbeToDst]] for a given mem op /** Construct an appropriate [[uncore.ProbeToDst]] for a given mem op
* *
@ -200,7 +198,7 @@ class ManagerMetadata extends CoherenceMetadata {
* @param addr_block address of the cache block being probed * @param addr_block address of the cache block being probed
*/ */
def makeProbe(dst: UInt, op_code: UInt, addr_block: UInt): ProbeToDst = def makeProbe(dst: UInt, op_code: UInt, addr_block: UInt): ProbeToDst =
Bundle(Probe(dst, co.getProbeType(op_code, this), addr_block), { case TLId => id }) Bundle(Probe(dst, co.getProbeType(op_code, this), addr_block)(p))
/** Construct an appropriate [[uncore.ProbeToDst]] for an eviction /** Construct an appropriate [[uncore.ProbeToDst]] for an eviction
* *
@ -221,7 +219,7 @@ class ManagerMetadata extends CoherenceMetadata {
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
g_type = Grant.voluntaryAckType, g_type = Grant.voluntaryAckType,
client_xact_id = rel.client_xact_id, client_xact_id = rel.client_xact_id,
manager_xact_id = manager_xact_id), { case TLId => id }) manager_xact_id = manager_xact_id)(p))
} }
/** Construct an appropriate [[uncore.GrantToDst]] to respond to an [[uncore.Acquire]] /** Construct an appropriate [[uncore.GrantToDst]] to respond to an [[uncore.Acquire]]
@ -247,7 +245,7 @@ class ManagerMetadata extends CoherenceMetadata {
client_xact_id = acq.client_xact_id, client_xact_id = acq.client_xact_id,
manager_xact_id = manager_xact_id, manager_xact_id = manager_xact_id,
addr_beat = addr_beat, addr_beat = addr_beat,
data = data), { case TLId => id }) data = data)(p))
} }
/** Construct an [[uncore.GrantToDst]] to respond to an [[uncore.Acquire]] with some overrides /** Construct an [[uncore.GrantToDst]] to respond to an [[uncore.Acquire]] with some overrides
@ -275,31 +273,31 @@ class ManagerMetadata extends CoherenceMetadata {
* @param incoming the incoming [[uncore.ReleaseFromSrc]] * @param incoming the incoming [[uncore.ReleaseFromSrc]]
*/ */
def onRelease(incoming: ReleaseFromSrc): ManagerMetadata = def onRelease(incoming: ReleaseFromSrc): ManagerMetadata =
Bundle(co.managerMetadataOnRelease(incoming, incoming.client_id, this), { case TLId => id }) co.managerMetadataOnRelease(incoming, incoming.client_id, this)
/** New metadata after sending a [[uncore.GrantToDst]] /** New metadata after sending a [[uncore.GrantToDst]]
* *
* @param outgoing the outgoing [[uncore.GrantToDst]] * @param outgoing the outgoing [[uncore.GrantToDst]]
*/ */
def onGrant(outgoing: GrantToDst): ManagerMetadata = def onGrant(outgoing: GrantToDst): ManagerMetadata =
Bundle(co.managerMetadataOnGrant(outgoing, outgoing.client_id, this), { case TLId => id }) co.managerMetadataOnGrant(outgoing, outgoing.client_id, this)
} }
/** Factories for ManagerMetadata, including on reset */ /** Factories for ManagerMetadata, including on reset */
object ManagerMetadata { object ManagerMetadata {
def apply(sharers: UInt, state: UInt = UInt(width = 0)) = { def apply(sharers: UInt, state: UInt = UInt(width = 0))(implicit p: Parameters) = {
val meta = Wire(new ManagerMetadata) val meta = Wire(new ManagerMetadata)
//meta.state := state TODO: Fix 0-width wires in Chisel //meta.state := state TODO: Fix 0-width wires in Chisel
meta.sharers := sharers meta.sharers := sharers
meta meta
} }
def apply() = { def apply(implicit p: Parameters) = {
val meta = Wire(new ManagerMetadata) val meta = Wire(new ManagerMetadata)
//meta.state := UInt(width = 0) TODO: Fix 0-width wires in Chisel //meta.state := UInt(width = 0) TODO: Fix 0-width wires in Chisel
meta.sharers := meta.co.dir.flush meta.sharers := meta.co.dir.flush
meta meta
} }
def onReset = new ManagerMetadata().co.managerMetadataOnReset def onReset(implicit p: Parameters) = ManagerMetadata(p)
} }
/** HierarchicalMetadata is used in a cache in a multi-level memory hierarchy /** HierarchicalMetadata is used in a cache in a multi-level memory hierarchy
@ -310,9 +308,9 @@ object ManagerMetadata {
* applied by contextually mapping [[uncore.TLId]] to one of * applied by contextually mapping [[uncore.TLId]] to one of
* [[uncore.InnerTLId]] or [[uncore.OuterTLId]]. * [[uncore.InnerTLId]] or [[uncore.OuterTLId]].
*/ */
class HierarchicalMetadata extends CoherenceMetadata { class HierarchicalMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
val inner: ManagerMetadata = Bundle(new ManagerMetadata, {case TLId => params(InnerTLId)}) val inner: ManagerMetadata = Bundle(new ManagerMetadata()(p.alterPartial({case TLId => p(InnerTLId)})))
val outer: ClientMetadata = Bundle(new ClientMetadata, {case TLId => params(OuterTLId)}) val outer: ClientMetadata = Bundle(new ClientMetadata()(p.alterPartial({case TLId => p(OuterTLId)})))
def ===(rhs: HierarchicalMetadata): Bool = def ===(rhs: HierarchicalMetadata): Bool =
this.inner === rhs.inner && this.outer === rhs.outer this.inner === rhs.inner && this.outer === rhs.outer
def !=(rhs: HierarchicalMetadata): Bool = !this.===(rhs) def !=(rhs: HierarchicalMetadata): Bool = !this.===(rhs)
@ -320,13 +318,15 @@ class HierarchicalMetadata extends CoherenceMetadata {
/** Factories for HierarchicalMetadata, including on reset */ /** Factories for HierarchicalMetadata, including on reset */
object HierarchicalMetadata { object HierarchicalMetadata {
def apply(inner: ManagerMetadata, outer: ClientMetadata): HierarchicalMetadata = { def apply(inner: ManagerMetadata, outer: ClientMetadata)
(implicit p: Parameters): HierarchicalMetadata = {
val m = Wire(new HierarchicalMetadata) val m = Wire(new HierarchicalMetadata)
m.inner := inner m.inner := inner
m.outer := outer m.outer := outer
m m
} }
def onReset: HierarchicalMetadata = apply(ManagerMetadata.onReset, ClientMetadata.onReset) def onReset(implicit p: Parameters): HierarchicalMetadata =
apply(ManagerMetadata.onReset, ClientMetadata.onReset)
} }
/** Identifies the TLId of the inner network in a hierarchical cache controller */ /** Identifies the TLId of the inner network in a hierarchical cache controller */

22
uncore/src/main/scala/network.scala
View File

@ -45,22 +45,23 @@ class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Opti
abstract class LogicalNetwork extends Module abstract class LogicalNetwork extends Module
class LogicalHeader extends Bundle { class LogicalHeader(implicit p: Parameters) extends junctions.ParameterizedBundle()(p) {
val src = UInt(width = params(LNHeaderBits)) val src = UInt(width = p(LNHeaderBits))
val dst = UInt(width = params(LNHeaderBits)) val dst = UInt(width = p(LNHeaderBits))
} }
class LogicalNetworkIO[T <: Data](dType: T) extends Bundle { class LogicalNetworkIO[T <: Data](dType: T)(implicit p: Parameters) extends Bundle {
val header = new LogicalHeader val header = new LogicalHeader
val payload = dType.cloneType val payload = dType.cloneType
override def cloneType = new LogicalNetworkIO(dType).asInstanceOf[this.type] override def cloneType = new LogicalNetworkIO(dType)(p).asInstanceOf[this.type]
} }
object DecoupledLogicalNetworkIOWrapper { object DecoupledLogicalNetworkIOWrapper {
def apply[T <: Data]( def apply[T <: Data](
in: DecoupledIO[T], in: DecoupledIO[T],
src: UInt = UInt(0), src: UInt = UInt(0),
dst: UInt = UInt(0)): DecoupledIO[LogicalNetworkIO[T]] = { dst: UInt = UInt(0))
(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
val out = Wire(Decoupled(new LogicalNetworkIO(in.bits))) val out = Wire(Decoupled(new LogicalNetworkIO(in.bits)))
out.valid := in.valid out.valid := in.valid
out.bits.payload := in.bits out.bits.payload := in.bits
@ -72,7 +73,8 @@ object DecoupledLogicalNetworkIOWrapper {
} }
object DecoupledLogicalNetworkIOUnwrapper { object DecoupledLogicalNetworkIOUnwrapper {
def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]]): DecoupledIO[T] = { def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]])
(implicit p: Parameters): DecoupledIO[T] = {
val out = Wire(Decoupled(in.bits.payload)) val out = Wire(Decoupled(in.bits.payload))
out.valid := in.valid out.valid := in.valid
out.bits := in.bits.payload out.bits := in.bits.payload
@ -82,7 +84,8 @@ object DecoupledLogicalNetworkIOUnwrapper {
} }
object DefaultFromPhysicalShim { object DefaultFromPhysicalShim {
def apply[T <: Data](in: DecoupledIO[PhysicalNetworkIO[T]]): DecoupledIO[LogicalNetworkIO[T]] = { def apply[T <: Data](in: DecoupledIO[PhysicalNetworkIO[T]])
(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
val out = Wire(Decoupled(new LogicalNetworkIO(in.bits.payload))) val out = Wire(Decoupled(new LogicalNetworkIO(in.bits.payload)))
out.bits.header := in.bits.header out.bits.header := in.bits.header
out.bits.payload := in.bits.payload out.bits.payload := in.bits.payload
@ -93,7 +96,8 @@ object DefaultFromPhysicalShim {
} }
object DefaultToPhysicalShim { object DefaultToPhysicalShim {
def apply[T <: Data](n: Int, in: DecoupledIO[LogicalNetworkIO[T]]): DecoupledIO[PhysicalNetworkIO[T]] = { def apply[T <: Data](n: Int, in: DecoupledIO[LogicalNetworkIO[T]])
(implicit p: Parameters): DecoupledIO[PhysicalNetworkIO[T]] = {
val out = Wire(Decoupled(new PhysicalNetworkIO(n, in.bits.payload))) val out = Wire(Decoupled(new PhysicalNetworkIO(n, in.bits.payload)))
out.bits.header := in.bits.header out.bits.header := in.bits.header
out.bits.payload := in.bits.payload out.bits.payload := in.bits.payload

12
uncore/src/main/scala/rtc.scala
View File

@ -3,17 +3,19 @@ package uncore
import Chisel._ import Chisel._
import junctions._ import junctions._
class RTC(pcr_MTIME: Int)(implicit val p: Parameters) extends Module with HTIFParameters { case object RTCPeriod extends Field[Int]
class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule {
val io = new NastiIO val io = new NastiIO
private val addrMap = new AddrHashMap(params(NastiAddrMap)) private val addrMap = new AddrHashMap(p(NastiAddrMap))
val addrTable = Vec.tabulate(nCores) { i => val addrTable = Vec.tabulate(nCores) { i =>
UInt(addrMap(s"conf:csr$i").start + pcr_MTIME * scrDataBytes) UInt(addrMap(s"conf:csr$i").start + csr_MTIME * scrDataBytes)
} }
val rtc = Reg(init=UInt(0,64)) val rtc = Reg(init=UInt(0, scrDataBits))
val rtc_tick = Counter(params(RTCPeriod)).inc() val rtc_tick = Counter(p(RTCPeriod)).inc()
val sending_addr = Reg(init = Bool(false)) val sending_addr = Reg(init = Bool(false))
val sending_data = Reg(init = Bool(false)) val sending_data = Reg(init = Bool(false))

14
uncore/src/main/scala/scr.scala
View File

@ -3,24 +3,24 @@ package uncore
import Chisel._ import Chisel._
import junctions.{SMIIO, MMIOBase} import junctions.{SMIIO, MMIOBase}
class SCRIO extends HTIFBundle { class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
val rdata = Vec(Bits(INPUT, 64), nSCR) val rdata = Vec(Bits(INPUT, scrDataBits), nSCR)
val wen = Bool(OUTPUT) val wen = Bool(OUTPUT)
val waddr = UInt(OUTPUT, log2Up(nSCR)) val waddr = UInt(OUTPUT, log2Up(nSCR))
val wdata = Bits(OUTPUT, 64) val wdata = Bits(OUTPUT, scrDataBits)
} }
class SCRFile extends Module with HTIFParameters { class SCRFile(implicit p: Parameters) extends HtifModule()(p) {
val io = new Bundle { val io = new Bundle {
val smi = new SMIIO(64, scrAddrBits).flip val smi = new SMIIO(scrDataBits, scrAddrBits).flip
val scr = new SCRIO val scr = new SCRIO
} }
val scr_rdata = Wire(Vec(Bits(width=64), io.scr.rdata.size)) val scr_rdata = Wire(Vec(Bits(width=scrDataBits), io.scr.rdata.size))
for (i <- 0 until scr_rdata.size) for (i <- 0 until scr_rdata.size)
scr_rdata(i) := io.scr.rdata(i) scr_rdata(i) := io.scr.rdata(i)
scr_rdata(0) := UInt(nCores) scr_rdata(0) := UInt(nCores)
scr_rdata(1) := UInt(params(MMIOBase) >> 20) scr_rdata(1) := UInt(p(MMIOBase) >> 20)
val read_addr = Reg(init = UInt(0, scrAddrBits)) val read_addr = Reg(init = UInt(0, scrAddrBits))
val resp_valid = Reg(init = Bool(false)) val resp_valid = Reg(init = Bool(false))

228
uncore/src/main/scala/tilelink.scala
View File

@ -38,24 +38,25 @@ case object TLNetworkIsOrderedP2P extends Field[Boolean]
case object TLWriteMaskBits extends Field[Int] case object TLWriteMaskBits extends Field[Int]
/** Utility trait for building Modules and Bundles that use TileLink parameters */ /** Utility trait for building Modules and Bundles that use TileLink parameters */
trait TileLinkParameters extends UsesParameters { trait HasTileLinkParameters {
val tlCoh = params(TLCoherencePolicy) implicit val p: Parameters
val tlNManagers = params(TLNManagers) val tlCoh = p(TLCoherencePolicy)
val tlNClients = params(TLNClients) val tlNManagers = p(TLNManagers)
val tlNCachingClients = params(TLNCachingClients) val tlNClients = p(TLNClients)
val tlNCachelessClients = params(TLNCachelessClients) val tlNCachingClients = p(TLNCachingClients)
val tlNCachelessClients = p(TLNCachelessClients)
val tlClientIdBits = log2Up(tlNClients) val tlClientIdBits = log2Up(tlNClients)
val tlManagerIdBits = log2Up(tlNManagers) val tlManagerIdBits = log2Up(tlNManagers)
val tlMaxClientXacts = params(TLMaxClientXacts) val tlMaxClientXacts = p(TLMaxClientXacts)
val tlMaxClientsPerPort = params(TLMaxClientsPerPort) val tlMaxClientsPerPort = p(TLMaxClientsPerPort)
val tlMaxManagerXacts = params(TLMaxManagerXacts) val tlMaxManagerXacts = p(TLMaxManagerXacts)
val tlClientXactIdBits = log2Up(tlMaxClientXacts*tlMaxClientsPerPort) val tlClientXactIdBits = log2Up(tlMaxClientXacts*tlMaxClientsPerPort)
val tlManagerXactIdBits = log2Up(tlMaxManagerXacts) val tlManagerXactIdBits = log2Up(tlMaxManagerXacts)
val tlBlockAddrBits = params(TLBlockAddrBits) val tlBlockAddrBits = p(TLBlockAddrBits)
val tlDataBits = params(TLDataBits) val tlDataBits = p(TLDataBits)
val tlDataBytes = tlDataBits/8 val tlDataBytes = tlDataBits/8
val tlDataBeats = params(TLDataBeats) val tlDataBeats = p(TLDataBeats)
val tlWriteMaskBits = params(TLWriteMaskBits) val tlWriteMaskBits = p(TLWriteMaskBits)
val tlBeatAddrBits = log2Up(tlDataBeats) val tlBeatAddrBits = log2Up(tlDataBeats)
val tlByteAddrBits = log2Up(tlWriteMaskBits) val tlByteAddrBits = log2Up(tlWriteMaskBits)
val tlMemoryOpcodeBits = M_SZ val tlMemoryOpcodeBits = M_SZ
@ -68,32 +69,34 @@ trait TileLinkParameters extends UsesParameters {
tlMemoryOpcodeBits)) + 1 tlMemoryOpcodeBits)) + 1
val tlGrantTypeBits = max(log2Up(Grant.nBuiltInTypes), val tlGrantTypeBits = max(log2Up(Grant.nBuiltInTypes),
tlCoh.grantTypeWidth) + 1 tlCoh.grantTypeWidth) + 1
val tlNetworkPreservesPointToPointOrdering = params(TLNetworkIsOrderedP2P) val tlNetworkPreservesPointToPointOrdering = p(TLNetworkIsOrderedP2P)
val tlNetworkDoesNotInterleaveBeats = true val tlNetworkDoesNotInterleaveBeats = true
val amoAluOperandBits = params(AmoAluOperandBits) val amoAluOperandBits = p(AmoAluOperandBits)
} }
abstract class TLBundle extends Bundle with TileLinkParameters abstract class TLModule(implicit val p: Parameters) extends Module
abstract class TLModule extends Module with TileLinkParameters with HasTileLinkParameters
abstract class TLBundle(implicit val p: Parameters) extends junctions.ParameterizedBundle()(p)
with HasTileLinkParameters
/** Base trait for all TileLink channels */ /** Base trait for all TileLink channels */
trait TileLinkChannel extends TLBundle { abstract class TileLinkChannel(implicit p: Parameters) extends TLBundle()(p) {
def hasData(dummy: Int = 0): Bool def hasData(dummy: Int = 0): Bool
def hasMultibeatData(dummy: Int = 0): Bool def hasMultibeatData(dummy: Int = 0): Bool
} }
/** Directionality of message channel. Used to hook up logical network ports to physical network ports */ /** Directionality of message channel. Used to hook up logical network ports to physical network ports */
trait ClientToManagerChannel extends TileLinkChannel abstract class ClientToManagerChannel(implicit p: Parameters) extends TileLinkChannel()(p)
/** Directionality of message channel. Used to hook up logical network ports to physical network ports */ /** Directionality of message channel. Used to hook up logical network ports to physical network ports */
trait ManagerToClientChannel extends TileLinkChannel abstract class ManagerToClientChannel(implicit p: Parameters) extends TileLinkChannel()(p)
/** Directionality of message channel. Used to hook up logical network ports to physical network ports */ /** Directionality of message channel. Used to hook up logical network ports to physical network ports */
trait ClientToClientChannel extends TileLinkChannel // Unused for now abstract class ClientToClientChannel(implicit p: Parameters) extends TileLinkChannel()(p) // Unused for now
/** Common signals that are used in multiple channels. /** Common signals that are used in multiple channels.
* These traits are useful for type parameterizing bundle wiring functions. * These traits are useful for type parameterizing bundle wiring functions.
*/ */
/** Address of a cache block. */ /** Address of a cache block. */
trait HasCacheBlockAddress extends TLBundle { trait HasCacheBlockAddress extends HasTileLinkParameters {
val addr_block = UInt(width = tlBlockAddrBits) val addr_block = UInt(width = tlBlockAddrBits)
def conflicts(that: HasCacheBlockAddress) = this.addr_block === that.addr_block def conflicts(that: HasCacheBlockAddress) = this.addr_block === that.addr_block
@ -101,17 +104,17 @@ trait HasCacheBlockAddress extends TLBundle {
} }
/** Sub-block address or beat id of multi-beat data */ /** Sub-block address or beat id of multi-beat data */
trait HasTileLinkBeatId extends TLBundle { trait HasTileLinkBeatId extends HasTileLinkParameters {
val addr_beat = UInt(width = tlBeatAddrBits) val addr_beat = UInt(width = tlBeatAddrBits)
} }
/* Client-side transaction id. Usually Miss Status Handling Register File index */ /* Client-side transaction id. Usually Miss Status Handling Register File index */
trait HasClientTransactionId extends TLBundle { trait HasClientTransactionId extends HasTileLinkParameters {
val client_xact_id = Bits(width = tlClientXactIdBits) val client_xact_id = Bits(width = tlClientXactIdBits)
} }
/** Manager-side transaction id. Usually Transaction Status Handling Register File index. */ /** Manager-side transaction id. Usually Transaction Status Handling Register File index. */
trait HasManagerTransactionId extends TLBundle { trait HasManagerTransactionId extends HasTileLinkParameters {
val manager_xact_id = Bits(width = tlManagerXactIdBits) val manager_xact_id = Bits(width = tlManagerXactIdBits)
} }
@ -124,7 +127,7 @@ trait HasTileLinkData extends HasTileLinkBeatId {
} }
/** The id of a client source or destination. Used in managers. */ /** The id of a client source or destination. Used in managers. */
trait HasClientId extends TLBundle { trait HasClientId extends HasTileLinkParameters {
val client_id = UInt(width = tlClientIdBits) val client_id = UInt(width = tlClientIdBits)
} }
@ -138,7 +141,7 @@ trait HasClientId extends TLBundle {
* PutAtomic built-in types. After sending an Acquire, clients must * PutAtomic built-in types. After sending an Acquire, clients must
* wait for a manager to send them a [[uncore.Grant]] message in response. * wait for a manager to send them a [[uncore.Grant]] message in response.
*/ */
class Acquire extends ClientToManagerChannel class Acquire(implicit p: Parameters) extends ClientToManagerChannel()(p)
with HasCacheBlockAddress with HasCacheBlockAddress
with HasClientTransactionId with HasClientTransactionId
with HasTileLinkData { with HasTileLinkData {
@ -219,7 +222,7 @@ class Acquire extends ClientToManagerChannel
} }
/** [[uncore.Acquire]] with an extra field stating its source id */ /** [[uncore.Acquire]] with an extra field stating its source id */
class AcquireFromSrc extends Acquire with HasClientId class AcquireFromSrc(implicit p: Parameters) extends Acquire()(p) with HasClientId
/** Contains definitions of the the built-in Acquire types and a factory /** Contains definitions of the the built-in Acquire types and a factory
* for [[uncore.Acquire]] * for [[uncore.Acquire]]
@ -249,7 +252,7 @@ object Acquire {
def typesWithMultibeatData = Vec(putBlockType) def typesWithMultibeatData = Vec(putBlockType)
def typesOnSubBlocks = Vec(putType, getType, putAtomicType) def typesOnSubBlocks = Vec(putType, getType, putAtomicType)
def fullWriteMask = SInt(-1, width = new Acquire().tlWriteMaskBits).toUInt def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLWriteMaskBits)).toUInt
// Most generic constructor // Most generic constructor
def apply( def apply(
@ -259,7 +262,8 @@ object Acquire {
addr_block: UInt, addr_block: UInt,
addr_beat: UInt = UInt(0), addr_beat: UInt = UInt(0),
data: UInt = UInt(0), data: UInt = UInt(0),
union: UInt = UInt(0)): Acquire = { union: UInt = UInt(0))
(implicit p: Parameters): Acquire = {
val acq = Wire(new Acquire) val acq = Wire(new Acquire)
acq.is_builtin_type := is_builtin_type acq.is_builtin_type := is_builtin_type
acq.a_type := a_type acq.a_type := a_type
@ -272,7 +276,7 @@ object Acquire {
} }
// Copy constructor // Copy constructor
def apply(a: Acquire): Acquire = { def apply(a: Acquire): Acquire = {
val acq = Wire(new Acquire) val acq = Wire(new Acquire()(a.p))
acq := a acq := a
acq acq
} }
@ -295,7 +299,8 @@ object Get {
client_xact_id: UInt, client_xact_id: UInt,
addr_block: UInt, addr_block: UInt,
addr_beat: UInt, addr_beat: UInt,
alloc: Bool = Bool(true)): Acquire = { alloc: Bool = Bool(true))
(implicit p: Parameters): Acquire = {
Acquire( Acquire(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
a_type = Acquire.getType, a_type = Acquire.getType,
@ -310,7 +315,8 @@ object Get {
addr_beat: UInt, addr_beat: UInt,
addr_byte: UInt, addr_byte: UInt,
operand_size: UInt, operand_size: UInt,
alloc: Bool): Acquire = { alloc: Bool)
(implicit p: Parameters): Acquire = {
Acquire( Acquire(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
a_type = Acquire.getType, a_type = Acquire.getType,
@ -334,7 +340,8 @@ object GetBlock {
def apply( def apply(
client_xact_id: UInt = UInt(0), client_xact_id: UInt = UInt(0),
addr_block: UInt, addr_block: UInt,
alloc: Bool = Bool(true)): Acquire = { alloc: Bool = Bool(true))
(implicit p: Parameters): Acquire = {
Acquire( Acquire(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
a_type = Acquire.getBlockType, a_type = Acquire.getBlockType,
@ -353,7 +360,8 @@ object GetBlock {
object GetPrefetch { object GetPrefetch {
def apply( def apply(
client_xact_id: UInt, client_xact_id: UInt,
addr_block: UInt): Acquire = { addr_block: UInt)
(implicit p: Parameters): Acquire = {
Acquire( Acquire(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
a_type = Acquire.prefetchType, a_type = Acquire.prefetchType,
@ -380,7 +388,8 @@ object Put {
addr_block: UInt, addr_block: UInt,
addr_beat: UInt, addr_beat: UInt,
data: UInt, data: UInt,
wmask: UInt = Acquire.fullWriteMask): Acquire = { wmask: Option[UInt]= None)
(implicit p: Parameters): Acquire = {
Acquire( Acquire(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
a_type = Acquire.putType, a_type = Acquire.putType,
@ -388,7 +397,7 @@ object Put {
addr_beat = addr_beat, addr_beat = addr_beat,
client_xact_id = client_xact_id, client_xact_id = client_xact_id,
data = data, data = data,
union = Cat(wmask, Bool(true))) union = Cat(wmask.getOrElse(Acquire.fullWriteMask), Bool(true)))
} }
} }
@ -411,7 +420,8 @@ object PutBlock {
addr_block: UInt, addr_block: UInt,
addr_beat: UInt, addr_beat: UInt,
data: UInt, data: UInt,
wmask: UInt): Acquire = { wmask: UInt)
(implicit p: Parameters): Acquire = {
Acquire( Acquire(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
a_type = Acquire.putBlockType, a_type = Acquire.putBlockType,
@ -426,7 +436,8 @@ object PutBlock {
addr_block: UInt, addr_block: UInt,
addr_beat: UInt, addr_beat: UInt,
data: UInt, data: UInt,
alloc: Bool = Bool(true)): Acquire = { alloc: Bool = Bool(true))
(implicit p: Parameters): Acquire = {
Acquire( Acquire(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
a_type = Acquire.putBlockType, a_type = Acquire.putBlockType,
@ -447,7 +458,8 @@ object PutBlock {
object PutPrefetch { object PutPrefetch {
def apply( def apply(
client_xact_id: UInt, client_xact_id: UInt,
addr_block: UInt): Acquire = { addr_block: UInt)
(implicit p: Parameters): Acquire = {
Acquire( Acquire(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
a_type = Acquire.prefetchType, a_type = Acquire.prefetchType,
@ -476,7 +488,8 @@ object PutAtomic {
addr_byte: UInt, addr_byte: UInt,
atomic_opcode: UInt, atomic_opcode: UInt,
operand_size: UInt, operand_size: UInt,
data: UInt): Acquire = { data: UInt)
(implicit p: Parameters): Acquire = {
Acquire( Acquire(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
a_type = Acquire.putAtomicType, a_type = Acquire.putAtomicType,
@ -493,7 +506,7 @@ object PutAtomic {
* The available types of Probes are customized by a particular * The available types of Probes are customized by a particular
* [[uncore.CoherencePolicy]]. * [[uncore.CoherencePolicy]].
*/ */
class Probe extends ManagerToClientChannel class Probe(implicit p: Parameters) extends ManagerToClientChannel()(p)
with HasCacheBlockAddress { with HasCacheBlockAddress {
val p_type = UInt(width = tlCoh.probeTypeWidth) val p_type = UInt(width = tlCoh.probeTypeWidth)
@ -503,7 +516,7 @@ class Probe extends ManagerToClientChannel
} }
/** [[uncore.Probe]] with an extra field stating its destination id */ /** [[uncore.Probe]] with an extra field stating its destination id */
class ProbeToDst extends Probe with HasClientId class ProbeToDst(implicit p: Parameters) extends Probe()(p) with HasClientId
/** Contains factories for [[uncore.Probe]] and [[uncore.ProbeToDst]] /** Contains factories for [[uncore.Probe]] and [[uncore.ProbeToDst]]
* *
@ -515,13 +528,13 @@ class ProbeToDst extends Probe with HasClientId
* @param addr_block address of the cache block * @param addr_block address of the cache block
*/ */
object Probe { object Probe {
def apply(p_type: UInt, addr_block: UInt): Probe = { def apply(p_type: UInt, addr_block: UInt)(implicit p: Parameters): Probe = {
val prb = Wire(new Probe) val prb = Wire(new Probe)
prb.p_type := p_type prb.p_type := p_type
prb.addr_block := addr_block prb.addr_block := addr_block
prb prb
} }
def apply(dst: UInt, p_type: UInt, addr_block: UInt): ProbeToDst = { def apply(dst: UInt, p_type: UInt, addr_block: UInt)(implicit p: Parameters): ProbeToDst = {
val prb = Wire(new ProbeToDst) val prb = Wire(new ProbeToDst)
prb.client_id := dst prb.client_id := dst
prb.p_type := p_type prb.p_type := p_type
@ -537,7 +550,7 @@ object Probe {
* a particular [[uncore.CoherencePolicy]]. Releases may contain data or may be * a particular [[uncore.CoherencePolicy]]. Releases may contain data or may be
* simple acknowledgements. Voluntary Releases are acknowledged with [[uncore.Grant Grants]]. * simple acknowledgements. Voluntary Releases are acknowledged with [[uncore.Grant Grants]].
*/ */
class Release extends ClientToManagerChannel class Release(implicit p: Parameters) extends ClientToManagerChannel()(p)
with HasCacheBlockAddress with HasCacheBlockAddress
with HasClientTransactionId with HasClientTransactionId
with HasTileLinkData { with HasTileLinkData {
@ -555,7 +568,7 @@ class Release extends ClientToManagerChannel
} }
/** [[uncore.Release]] with an extra field stating its source id */ /** [[uncore.Release]] with an extra field stating its source id */
class ReleaseFromSrc extends Release with HasClientId class ReleaseFromSrc(implicit p: Parameters) extends Release()(p) with HasClientId
/** Contains a [[uncore.Release]] factory /** Contains a [[uncore.Release]] factory
* *
@ -576,7 +589,8 @@ object Release {
client_xact_id: UInt, client_xact_id: UInt,
addr_block: UInt, addr_block: UInt,
addr_beat: UInt = UInt(0), addr_beat: UInt = UInt(0),
data: UInt = UInt(0)): Release = { data: UInt = UInt(0))
(implicit p: Parameters): Release = {
val rel = Wire(new Release) val rel = Wire(new Release)
rel.r_type := r_type rel.r_type := r_type
rel.client_xact_id := client_xact_id rel.client_xact_id := client_xact_id
@ -595,7 +609,7 @@ object Release {
* coherence policies may also define custom Grant types. Grants may contain data * coherence policies may also define custom Grant types. Grants may contain data
* or may be simple acknowledgements. Grants are responded to with [[uncore.Finish]]. * or may be simple acknowledgements. Grants are responded to with [[uncore.Finish]].
*/ */
class Grant extends ManagerToClientChannel class Grant(implicit p: Parameters) extends ManagerToClientChannel()(p)
with HasTileLinkData with HasTileLinkData
with HasClientTransactionId with HasClientTransactionId
with HasManagerTransactionId { with HasManagerTransactionId {
@ -616,14 +630,14 @@ class Grant extends ManagerToClientChannel
def isVoluntary(dummy: Int = 0): Bool = isBuiltInType() && (g_type === Grant.voluntaryAckType) def isVoluntary(dummy: Int = 0): Bool = isBuiltInType() && (g_type === Grant.voluntaryAckType)
def requiresAck(dummy: Int = 0): Bool = !Bool(tlNetworkPreservesPointToPointOrdering) && !isVoluntary() def requiresAck(dummy: Int = 0): Bool = !Bool(tlNetworkPreservesPointToPointOrdering) && !isVoluntary()
def makeFinish(dummy: Int = 0): Finish = { def makeFinish(dummy: Int = 0): Finish = {
val f = Wire(Bundle(new Finish, { case TLMaxManagerXacts => tlMaxManagerXacts })) val f = Wire(Bundle(new Finish))
f.manager_xact_id := this.manager_xact_id f.manager_xact_id := this.manager_xact_id
f f
} }
} }
/** [[uncore.Grant]] with an extra field stating its destination */ /** [[uncore.Grant]] with an extra field stating its destination */
class GrantToDst extends Grant with HasClientId class GrantToDst(implicit p: Parameters) extends Grant()(p) with HasClientId
/** Contains definitions of the the built-in grant types and factories /** Contains definitions of the the built-in grant types and factories
* for [[uncore.Grant]] and [[uncore.GrantToDst]] * for [[uncore.Grant]] and [[uncore.GrantToDst]]
@ -655,7 +669,8 @@ object Grant {
client_xact_id: UInt, client_xact_id: UInt,
manager_xact_id: UInt, manager_xact_id: UInt,
addr_beat: UInt, addr_beat: UInt,
data: UInt): Grant = { data: UInt)
(implicit p: Parameters): Grant = {
val gnt = Wire(new Grant) val gnt = Wire(new Grant)
gnt.is_builtin_type := is_builtin_type gnt.is_builtin_type := is_builtin_type
gnt.g_type := g_type gnt.g_type := g_type
@ -673,7 +688,8 @@ object Grant {
client_xact_id: UInt, client_xact_id: UInt,
manager_xact_id: UInt, manager_xact_id: UInt,
addr_beat: UInt = UInt(0), addr_beat: UInt = UInt(0),
data: UInt = UInt(0)): GrantToDst = { data: UInt = UInt(0))
(implicit p: Parameters): GrantToDst = {
val gnt = Wire(new GrantToDst) val gnt = Wire(new GrantToDst)
gnt.client_id := dst gnt.client_id := dst
gnt.is_builtin_type := is_builtin_type gnt.is_builtin_type := is_builtin_type
@ -692,20 +708,21 @@ object Grant {
* When a Finish message is received, a manager knows it is safe to begin * When a Finish message is received, a manager knows it is safe to begin
* processing other transactions that touch the same cache block. * processing other transactions that touch the same cache block.
*/ */
class Finish extends ClientToManagerChannel with HasManagerTransactionId { class Finish(implicit p: Parameters) extends ClientToManagerChannel()(p)
with HasManagerTransactionId {
def hasData(dummy: Int = 0) = Bool(false) def hasData(dummy: Int = 0) = Bool(false)
def hasMultibeatData(dummy: Int = 0) = Bool(false) def hasMultibeatData(dummy: Int = 0) = Bool(false)
} }
/** Complete IO definition for incoherent TileLink, including networking headers */ /** Complete IO definition for incoherent TileLink, including networking headers */
class UncachedTileLinkIO extends TLBundle { class UncachedTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
val acquire = new DecoupledIO(new LogicalNetworkIO(new Acquire)) val acquire = new DecoupledIO(new LogicalNetworkIO(new Acquire))
val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
val finish = new DecoupledIO(new LogicalNetworkIO(new Finish)) val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
} }
/** Complete IO definition for coherent TileLink, including networking headers */ /** Complete IO definition for coherent TileLink, including networking headers */
class TileLinkIO extends UncachedTileLinkIO { class TileLinkIO(implicit p: Parameters) extends UncachedTileLinkIO()(p) {
val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip
val release = new DecoupledIO(new LogicalNetworkIO(new Release)) val release = new DecoupledIO(new LogicalNetworkIO(new Release))
} }
@ -722,7 +739,7 @@ class TileLinkIO extends UncachedTileLinkIO {
* assumption that a [[uncore.FinishUnit]] has been coupled to the TileLinkIO port * assumption that a [[uncore.FinishUnit]] has been coupled to the TileLinkIO port
* to deal with acking received [[uncore.Grant Grants]]. * to deal with acking received [[uncore.Grant Grants]].
*/ */
class ClientUncachedTileLinkIO extends TLBundle { class ClientUncachedTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
val acquire = new DecoupledIO(new Acquire) val acquire = new DecoupledIO(new Acquire)
val grant = new DecoupledIO(new Grant).flip val grant = new DecoupledIO(new Grant).flip
} }
@ -730,7 +747,7 @@ class ClientUncachedTileLinkIO extends TLBundle {
/** This version of TileLinkIO does not contain network headers. /** This version of TileLinkIO does not contain network headers.
* It is intended for use within client agents. * It is intended for use within client agents.
*/ */
class ClientTileLinkIO extends ClientUncachedTileLinkIO { class ClientTileLinkIO(implicit p: Parameters) extends ClientUncachedTileLinkIO()(p) {
val probe = new DecoupledIO(new Probe).flip val probe = new DecoupledIO(new Probe).flip
val release = new DecoupledIO(new Release) val release = new DecoupledIO(new Release)
} }
@ -749,7 +766,7 @@ class ClientTileLinkIO extends ClientUncachedTileLinkIO {
* see Finished so they know when to allow new transactions on a cache * see Finished so they know when to allow new transactions on a cache
* block to proceed. * block to proceed.
*/ */
class ManagerTileLinkIO extends TLBundle { class ManagerTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
val acquire = new DecoupledIO(new AcquireFromSrc).flip val acquire = new DecoupledIO(new AcquireFromSrc).flip
val grant = new DecoupledIO(new GrantToDst) val grant = new DecoupledIO(new GrantToDst)
val finish = new DecoupledIO(new Finish).flip val finish = new DecoupledIO(new Finish).flip
@ -759,31 +776,21 @@ class ManagerTileLinkIO extends TLBundle {
/** Utilities for safely wrapping a *UncachedTileLink by pinning probe.ready and release.valid low */ /** Utilities for safely wrapping a *UncachedTileLink by pinning probe.ready and release.valid low */
object TileLinkIOWrapper { object TileLinkIOWrapper {
def apply(utl: ClientUncachedTileLinkIO, p: Parameters): ClientTileLinkIO = { def apply(tl: ClientUncachedTileLinkIO)(implicit p: Parameters): ClientTileLinkIO = {
val conv = Module(new ClientTileLinkIOWrapper)(p) val conv = Module(new ClientTileLinkIOWrapper)
conv.io.in <> utl conv.io.in <> tl
conv.io.out conv.io.out
} }
def apply(utl: ClientUncachedTileLinkIO): ClientTileLinkIO = { def apply(tl: UncachedTileLinkIO)(implicit p: Parameters): TileLinkIO = {
val conv = Module(new ClientTileLinkIOWrapper) val conv = Module(new TileLinkIOWrapper)
conv.io.in <> utl conv.io.in <> tl
conv.io.out conv.io.out
} }
def apply(tl: ClientTileLinkIO): ClientTileLinkIO = tl def apply(tl: ClientTileLinkIO): ClientTileLinkIO = tl
def apply(utl: UncachedTileLinkIO, p: Parameters): TileLinkIO = {
val conv = Module(new TileLinkIOWrapper)(p)
conv.io.in <> utl
conv.io.out
}
def apply(utl: UncachedTileLinkIO): TileLinkIO = {
val conv = Module(new TileLinkIOWrapper)
conv.io.in <> utl
conv.io.out
}
def apply(tl: TileLinkIO): TileLinkIO = tl def apply(tl: TileLinkIO): TileLinkIO = tl
} }
class TileLinkIOWrapper extends TLModule { class TileLinkIOWrapper(implicit p: Parameters) extends TLModule()(p) {
val io = new Bundle { val io = new Bundle {
val in = new UncachedTileLinkIO().flip val in = new UncachedTileLinkIO().flip
val out = new TileLinkIO val out = new TileLinkIO
@ -795,7 +802,7 @@ class TileLinkIOWrapper extends TLModule {
io.out.release.valid := Bool(false) io.out.release.valid := Bool(false)
} }
class ClientTileLinkIOWrapper extends TLModule { class ClientTileLinkIOWrapper(implicit p: Parameters) extends TLModule()(p) {
val io = new Bundle { val io = new Bundle {
val in = new ClientUncachedTileLinkIO().flip val in = new ClientUncachedTileLinkIO().flip
val out = new ClientTileLinkIO val out = new ClientTileLinkIO
@ -809,14 +816,16 @@ class ClientTileLinkIOWrapper extends TLModule {
/** Used to track metadata for transactions where multiple secondary misses have been merged /** Used to track metadata for transactions where multiple secondary misses have been merged
* and handled by a single transaction tracker. * and handled by a single transaction tracker.
*/ */
class SecondaryMissInfo extends TLBundle // TODO: add a_type to merge e.g. Get+GetBlocks, and/or HasClientId class SecondaryMissInfo(implicit p: Parameters) extends TLBundle()(p)
with HasTileLinkBeatId with HasTileLinkBeatId
with HasClientTransactionId with HasClientTransactionId
// TODO: add a_type to merge e.g. Get+GetBlocks, and/or HasClientId
/** A helper module that automatically issues [[uncore.Finish]] messages in repsonse /** A helper module that automatically issues [[uncore.Finish]] messages in repsonse
* to [[uncore.Grant]] that it receives from a manager and forwards to a client * to [[uncore.Grant]] that it receives from a manager and forwards to a client
*/ */
class FinishUnit(srcId: Int = 0, outstanding: Int = 2) extends TLModule with HasDataBeatCounters { class FinishUnit(srcId: Int = 0, outstanding: Int = 2)(implicit p: Parameters) extends TLModule()(p)
with HasDataBeatCounters {
val io = new Bundle { val io = new Bundle {
val grant = Decoupled(new LogicalNetworkIO(new Grant)).flip val grant = Decoupled(new LogicalNetworkIO(new Grant)).flip
val refill = Decoupled(new Grant) val refill = Decoupled(new Grant)
@ -862,12 +871,12 @@ class FinishUnit(srcId: Int = 0, outstanding: Int = 2) extends TLModule with Has
} }
} }
class FinishQueueEntry extends TLBundle { class FinishQueueEntry(implicit p: Parameters) extends TLBundle()(p) {
val fin = new Finish val fin = new Finish
val dst = UInt(width = log2Up(params(LNEndpoints))) val dst = UInt(width = log2Up(p(LNEndpoints)))
} }
class FinishQueue(entries: Int) extends Queue(new FinishQueueEntry, entries) class FinishQueue(entries: Int)(implicit p: Parameters) extends Queue(new FinishQueueEntry()(p), entries)
/** A port to convert [[uncore.ClientTileLinkIO]].flip into [[uncore.TileLinkIO]] /** A port to convert [[uncore.ClientTileLinkIO]].flip into [[uncore.TileLinkIO]]
* *
@ -879,7 +888,8 @@ class FinishQueue(entries: Int) extends Queue(new FinishQueueEntry, entries)
* @param clientId network port id of this agent * @param clientId network port id of this agent
* @param addrConvert how a physical address maps to a destination manager port id * @param addrConvert how a physical address maps to a destination manager port id
*/ */
class ClientTileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt) extends TLModule { class ClientTileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt)
(implicit p: Parameters) extends TLModule()(p) {
val io = new Bundle { val io = new Bundle {
val client = new ClientTileLinkIO().flip val client = new ClientTileLinkIO().flip
val network = new TileLinkIO val network = new TileLinkIO
@ -906,7 +916,8 @@ object ClientTileLinkHeaderCreator {
def apply[T <: ClientToManagerChannel with HasCacheBlockAddress]( def apply[T <: ClientToManagerChannel with HasCacheBlockAddress](
in: DecoupledIO[T], in: DecoupledIO[T],
clientId: Int, clientId: Int,
addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = { addrConvert: UInt => UInt)
(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits))) val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
out.bits.payload := in.bits out.bits.payload := in.bits
out.bits.header.src := UInt(clientId) out.bits.header.src := UInt(clientId)
@ -927,7 +938,8 @@ object ClientTileLinkHeaderCreator {
* @param managerId the network port id of this agent * @param managerId the network port id of this agent
* @param idConvert how a sharer id maps to a destination client port id * @param idConvert how a sharer id maps to a destination client port id
*/ */
class ManagerTileLinkNetworkPort(managerId: Int, idConvert: UInt => UInt) extends TLModule { class ManagerTileLinkNetworkPort(managerId: Int, idConvert: UInt => UInt)
(implicit p: Parameters) extends TLModule()(p) {
val io = new Bundle { val io = new Bundle {
val manager = new ManagerTileLinkIO().flip val manager = new ManagerTileLinkIO().flip
val network = new TileLinkIO().flip val network = new TileLinkIO().flip
@ -945,7 +957,8 @@ object ManagerTileLinkHeaderCreator {
def apply[T <: ManagerToClientChannel with HasClientId]( def apply[T <: ManagerToClientChannel with HasClientId](
in: DecoupledIO[T], in: DecoupledIO[T],
managerId: Int, managerId: Int,
idConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = { idConvert: UInt => UInt)
(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits))) val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
out.bits.payload := in.bits out.bits.payload := in.bits
out.bits.header.src := UInt(managerId) out.bits.header.src := UInt(managerId)
@ -960,7 +973,7 @@ object ManagerTileLinkHeaderCreator {
case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int) case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int)
/** Optionally enqueues each [[uncore.TileLinkChannel]] individually */ /** Optionally enqueues each [[uncore.TileLinkChannel]] individually */
class TileLinkEnqueuer(depths: TileLinkDepths) extends Module { class TileLinkEnqueuer(depths: TileLinkDepths)(implicit p: Parameters) extends Module {
val io = new Bundle { val io = new Bundle {
val client = new TileLinkIO().flip val client = new TileLinkIO().flip
val manager = new TileLinkIO val manager = new TileLinkIO
@ -973,18 +986,18 @@ class TileLinkEnqueuer(depths: TileLinkDepths) extends Module {
} }
object TileLinkEnqueuer { object TileLinkEnqueuer {
def apply(in: TileLinkIO, depths: TileLinkDepths)(p: Parameters): TileLinkIO = { def apply(in: TileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): TileLinkIO = {
val t = Module(new TileLinkEnqueuer(depths))(p) val t = Module(new TileLinkEnqueuer(depths))
t.io.client <> in t.io.client <> in
t.io.manager t.io.manager
} }
def apply(in: TileLinkIO, depth: Int)(p: Parameters): TileLinkIO = { def apply(in: TileLinkIO, depth: Int)(implicit p: Parameters): TileLinkIO = {
apply(in, TileLinkDepths(depth, depth, depth, depth, depth))(p) apply(in, TileLinkDepths(depth, depth, depth, depth, depth))
} }
} }
/** Utility functions for constructing TileLinkIO arbiters */ /** Utility functions for constructing TileLinkIO arbiters */
trait TileLinkArbiterLike extends TileLinkParameters { trait TileLinkArbiterLike extends HasTileLinkParameters {
// Some shorthand type variables // Some shorthand type variables
type ManagerSourcedWithId = ManagerToClientChannel with HasClientTransactionId type ManagerSourcedWithId = ManagerToClientChannel with HasClientTransactionId
type ClientSourcedWithId = ClientToManagerChannel with HasClientTransactionId type ClientSourcedWithId = ClientToManagerChannel with HasClientTransactionId
@ -1086,7 +1099,8 @@ trait TileLinkArbiterLike extends TileLinkParameters {
} }
/** Abstract base case for any Arbiters that have UncachedTileLinkIOs */ /** Abstract base case for any Arbiters that have UncachedTileLinkIOs */
abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike { abstract class UncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module
with TileLinkArbiterLike {
val io = new Bundle { val io = new Bundle {
val in = Vec(new UncachedTileLinkIO, arbN).flip val in = Vec(new UncachedTileLinkIO, arbN).flip
val out = new UncachedTileLinkIO val out = new UncachedTileLinkIO
@ -1097,7 +1111,8 @@ abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with Tile
} }
/** Abstract base case for any Arbiters that have cached TileLinkIOs */ /** Abstract base case for any Arbiters that have cached TileLinkIOs */
abstract class TileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike { abstract class TileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module
with TileLinkArbiterLike {
val io = new Bundle { val io = new Bundle {
val in = Vec(new TileLinkIO, arbN).flip val in = Vec(new TileLinkIO, arbN).flip
val out = new TileLinkIO val out = new TileLinkIO
@ -1133,15 +1148,15 @@ trait UsesNewId extends TileLinkArbiterLike {
} }
// Now we can mix-in thevarious id-generation traits to make concrete arbiter classes // Now we can mix-in thevarious id-generation traits to make concrete arbiter classes
class UncachedTileLinkIOArbiterThatAppendsArbiterId(val n: Int) extends UncachedTileLinkIOArbiter(n) with AppendsArbiterId class UncachedTileLinkIOArbiterThatAppendsArbiterId(val n: Int)(implicit p: Parameters) extends UncachedTileLinkIOArbiter(n)(p) with AppendsArbiterId
class UncachedTileLinkIOArbiterThatPassesId(val n: Int) extends UncachedTileLinkIOArbiter(n) with PassesId class UncachedTileLinkIOArbiterThatPassesId(val n: Int)(implicit p: Parameters) extends UncachedTileLinkIOArbiter(n)(p) with PassesId
class UncachedTileLinkIOArbiterThatUsesNewId(val n: Int) extends UncachedTileLinkIOArbiter(n) with UsesNewId class UncachedTileLinkIOArbiterThatUsesNewId(val n: Int)(implicit p: Parameters) extends UncachedTileLinkIOArbiter(n)(p) with UsesNewId
class TileLinkIOArbiterThatAppendsArbiterId(val n: Int) extends TileLinkIOArbiter(n) with AppendsArbiterId class TileLinkIOArbiterThatAppendsArbiterId(val n: Int)(implicit p: Parameters) extends TileLinkIOArbiter(n)(p) with AppendsArbiterId
class TileLinkIOArbiterThatPassesId(val n: Int) extends TileLinkIOArbiter(n) with PassesId class TileLinkIOArbiterThatPassesId(val n: Int)(implicit p: Parameters) extends TileLinkIOArbiter(n)(p) with PassesId
class TileLinkIOArbiterThatUsesNewId(val n: Int) extends TileLinkIOArbiter(n) with UsesNewId class TileLinkIOArbiterThatUsesNewId(val n: Int)(implicit p: Parameters) extends TileLinkIOArbiter(n)(p) with UsesNewId
/** Concrete uncached client-side arbiter that appends the arbiter's port id to client_xact_id */ /** Concrete uncached client-side arbiter that appends the arbiter's port id to client_xact_id */
class ClientUncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId { class ClientUncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module with TileLinkArbiterLike with AppendsArbiterId {
val io = new Bundle { val io = new Bundle {
val in = Vec(new ClientUncachedTileLinkIO, arbN).flip val in = Vec(new ClientUncachedTileLinkIO, arbN).flip
val out = new ClientUncachedTileLinkIO val out = new ClientUncachedTileLinkIO
@ -1151,7 +1166,7 @@ class ClientUncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLin
} }
/** Concrete client-side arbiter that appends the arbiter's port id to client_xact_id */ /** Concrete client-side arbiter that appends the arbiter's port id to client_xact_id */
class ClientTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId { class ClientTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module with TileLinkArbiterLike with AppendsArbiterId {
val io = new Bundle { val io = new Bundle {
val in = Vec(new ClientTileLinkIO, arbN).flip val in = Vec(new ClientTileLinkIO, arbN).flip
val out = new ClientTileLinkIO val out = new ClientTileLinkIO
@ -1246,7 +1261,7 @@ class ClientTileLinkIOUnwrapperInfo extends Bundle {
val builtin = Bool() val builtin = Bool()
} }
class ClientTileLinkIOUnwrapper extends TLModule { class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
val io = new Bundle { val io = new Bundle {
val in = new ClientTileLinkIO().flip val in = new ClientTileLinkIO().flip
val out = new ClientUncachedTileLinkIO val out = new ClientUncachedTileLinkIO
@ -1328,12 +1343,13 @@ class ClientTileLinkIOUnwrapper extends TLModule {
io.in.probe.valid := Bool(false) io.in.probe.valid := Bool(false)
} }
class NastiIOTileLinkIOConverterInfo extends TLBundle { class NastiIOTileLinkIOConverterInfo(implicit p: Parameters) extends TLBundle()(p) {
val byteOff = UInt(width = tlByteAddrBits) val byteOff = UInt(width = tlByteAddrBits)
val subblock = Bool() val subblock = Bool()
} }
class NastiIOTileLinkIOConverter(implicit val p: Parameters) extends TLModule with HasNastiParameters { class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
with HasNastiParameters {
val io = new Bundle { val io = new Bundle {
val tl = new ClientUncachedTileLinkIO().flip val tl = new ClientUncachedTileLinkIO().flip
val nasti = new NastiIO val nasti = new NastiIO
@ -1349,7 +1365,7 @@ class NastiIOTileLinkIOConverter(implicit val p: Parameters) extends TLModule wi
MT_Q -> UInt(log2Up(tlDataBytes)))) MT_Q -> UInt(log2Up(tlDataBytes))))
val dataBits = tlDataBits*tlDataBeats val dataBits = tlDataBits*tlDataBeats
val dstIdBits = params(LNHeaderBits) val dstIdBits = p(LNHeaderBits)
require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats") require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NastiIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits) require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NastiIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits)

50
uncore/src/main/scala/uncore.scala
View File

@ -6,18 +6,18 @@ import Chisel._
case object NReleaseTransactors extends Field[Int] case object NReleaseTransactors extends Field[Int]
case object NProbeTransactors extends Field[Int] case object NProbeTransactors extends Field[Int]
case object NAcquireTransactors extends Field[Int] case object NAcquireTransactors extends Field[Int]
case object RTCPeriod extends Field[Int]
trait CoherenceAgentParameters extends UsesParameters { trait HasCoherenceAgentParameters {
implicit val p: Parameters
val nReleaseTransactors = 1 val nReleaseTransactors = 1
val nAcquireTransactors = params(NAcquireTransactors) val nAcquireTransactors = p(NAcquireTransactors)
val nTransactors = nReleaseTransactors + nAcquireTransactors val nTransactors = nReleaseTransactors + nAcquireTransactors
val outerTLParams = params.alterPartial({ case TLId => params(OuterTLId)}) val outerTLParams = p.alterPartial({ case TLId => p(OuterTLId)})
val outerDataBeats = outerTLParams(TLDataBeats) val outerDataBeats = outerTLParams(TLDataBeats)
val outerDataBits = outerTLParams(TLDataBits) val outerDataBits = outerTLParams(TLDataBits)
val outerBeatAddrBits = log2Up(outerDataBeats) val outerBeatAddrBits = log2Up(outerDataBeats)
val outerByteAddrBits = log2Up(outerDataBits/8) val outerByteAddrBits = log2Up(outerDataBits/8)
val innerTLParams = params.alterPartial({case TLId => params(InnerTLId)}) val innerTLParams = p.alterPartial({case TLId => p(InnerTLId)})
val innerDataBeats = innerTLParams(TLDataBeats) val innerDataBeats = innerTLParams(TLDataBeats)
val innerDataBits = innerTLParams(TLDataBits) val innerDataBits = innerTLParams(TLDataBits)
val innerWriteMaskBits = innerTLParams(TLWriteMaskBits) val innerWriteMaskBits = innerTLParams(TLWriteMaskBits)
@ -26,8 +26,10 @@ trait CoherenceAgentParameters extends UsesParameters {
require(outerDataBeats == innerDataBeats) //TODO: must fix all xact_data Vecs to remove this requirement require(outerDataBeats == innerDataBeats) //TODO: must fix all xact_data Vecs to remove this requirement
} }
abstract class CoherenceAgentBundle extends Bundle with CoherenceAgentParameters abstract class CoherenceAgentModule(implicit val p: Parameters) extends Module
abstract class CoherenceAgentModule extends Module with CoherenceAgentParameters with HasCoherenceAgentParameters
abstract class CoherenceAgentBundle(implicit val p: Parameters) extends junctions.ParameterizedBundle()(p)
with HasCoherenceAgentParameters
trait HasCoherenceAgentWiringHelpers { trait HasCoherenceAgentWiringHelpers {
def doOutputArbitration[T <: TileLinkChannel]( def doOutputArbitration[T <: TileLinkChannel](
@ -39,7 +41,7 @@ trait HasCoherenceAgentWiringHelpers {
arb.io.in <> ins arb.io.in <> ins
} }
def doInputRouting[T <: HasManagerTransactionId]( def doInputRouting[T <: Bundle with HasManagerTransactionId](
in: DecoupledIO[T], in: DecoupledIO[T],
outs: Seq[DecoupledIO[T]]) { outs: Seq[DecoupledIO[T]]) {
val idx = in.bits.manager_xact_id val idx = in.bits.manager_xact_id
@ -49,7 +51,7 @@ trait HasCoherenceAgentWiringHelpers {
} }
} }
trait HasInnerTLIO extends CoherenceAgentBundle { trait HasInnerTLIO extends HasCoherenceAgentParameters {
val inner = Bundle(new ManagerTileLinkIO)(innerTLParams) val inner = Bundle(new ManagerTileLinkIO)(innerTLParams)
val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput
def iacq(dummy: Int = 0) = inner.acquire.bits def iacq(dummy: Int = 0) = inner.acquire.bits
@ -59,13 +61,13 @@ trait HasInnerTLIO extends CoherenceAgentBundle {
def ifin(dummy: Int = 0) = inner.finish.bits def ifin(dummy: Int = 0) = inner.finish.bits
} }
trait HasUncachedOuterTLIO extends CoherenceAgentBundle { trait HasUncachedOuterTLIO extends HasCoherenceAgentParameters {
val outer = Bundle(new ClientUncachedTileLinkIO)(outerTLParams) val outer = Bundle(new ClientUncachedTileLinkIO)(outerTLParams)
def oacq(dummy: Int = 0) = outer.acquire.bits def oacq(dummy: Int = 0) = outer.acquire.bits
def ognt(dummy: Int = 0) = outer.grant.bits def ognt(dummy: Int = 0) = outer.grant.bits
} }
trait HasCachedOuterTLIO extends CoherenceAgentBundle { trait HasCachedOuterTLIO extends HasCoherenceAgentParameters {
val outer = Bundle(new ClientTileLinkIO)(outerTLParams) val outer = Bundle(new ClientTileLinkIO)(outerTLParams)
def oacq(dummy: Int = 0) = outer.acquire.bits def oacq(dummy: Int = 0) = outer.acquire.bits
def oprb(dummy: Int = 0) = outer.probe.bits def oprb(dummy: Int = 0) = outer.probe.bits
@ -73,25 +75,29 @@ trait HasCachedOuterTLIO extends CoherenceAgentBundle {
def ognt(dummy: Int = 0) = outer.grant.bits def ognt(dummy: Int = 0) = outer.grant.bits
} }
class ManagerTLIO extends HasInnerTLIO with HasUncachedOuterTLIO class ManagerTLIO(implicit p: Parameters) extends CoherenceAgentBundle()(p)
with HasInnerTLIO
with HasUncachedOuterTLIO
abstract class CoherenceAgent extends CoherenceAgentModule { abstract class CoherenceAgent(implicit p: Parameters) extends CoherenceAgentModule()(p) {
def innerTL: ManagerTileLinkIO def innerTL: ManagerTileLinkIO
def outerTL: ClientTileLinkIO def outerTL: ClientTileLinkIO
def incoherent: Vec[Bool] def incoherent: Vec[Bool]
} }
abstract class ManagerCoherenceAgent extends CoherenceAgent abstract class ManagerCoherenceAgent(implicit p: Parameters) extends CoherenceAgent()(p)
with HasCoherenceAgentWiringHelpers { with HasCoherenceAgentWiringHelpers {
val io = new ManagerTLIO val io = new ManagerTLIO
def innerTL = io.inner def innerTL = io.inner
def outerTL = TileLinkIOWrapper(io.outer, outerTLParams) def outerTL = TileLinkIOWrapper(io.outer)(outerTLParams)
def incoherent = io.incoherent def incoherent = io.incoherent
} }
class HierarchicalTLIO extends HasInnerTLIO with HasCachedOuterTLIO class HierarchicalTLIO(implicit p: Parameters) extends CoherenceAgentBundle()(p)
with HasInnerTLIO
with HasCachedOuterTLIO
abstract class HierarchicalCoherenceAgent extends CoherenceAgent { abstract class HierarchicalCoherenceAgent(implicit p: Parameters) extends CoherenceAgent()(p) {
val io = new HierarchicalTLIO val io = new HierarchicalTLIO
def innerTL = io.inner def innerTL = io.inner
def outerTL = io.outer def outerTL = io.outer
@ -104,10 +110,14 @@ trait HasTrackerConflictIO extends Bundle {
val has_release_match = Bool(OUTPUT) val has_release_match = Bool(OUTPUT)
} }
class ManagerXactTrackerIO extends ManagerTLIO with HasTrackerConflictIO class ManagerXactTrackerIO(implicit p: Parameters) extends ManagerTLIO()(p)
class HierarchicalXactTrackerIO extends HierarchicalTLIO with HasTrackerConflictIO with HasTrackerConflictIO
abstract class XactTracker extends CoherenceAgentModule with HasDataBeatCounters { class HierarchicalXactTrackerIO(implicit p: Parameters) extends HierarchicalTLIO()(p)
with HasTrackerConflictIO
abstract class XactTracker(implicit p: Parameters) extends CoherenceAgentModule()(p)
with HasDataBeatCounters {
def addPendingBitWhenBeat[T <: HasBeat](inc: Bool, in: T): UInt = def addPendingBitWhenBeat[T <: HasBeat](inc: Bool, in: T): UInt =
Fill(in.tlDataBeats, inc) & UIntToOH(in.addr_beat) Fill(in.tlDataBeats, inc) & UIntToOH(in.addr_beat)
def dropPendingBitWhenBeat[T <: HasBeat](dec: Bool, in: T): UInt = def dropPendingBitWhenBeat[T <: HasBeat](dec: Bool, in: T): UInt =

4
uncore/src/main/scala/util.scala
View File

@ -42,7 +42,7 @@ object ZCounter {
} }
} }
class FlowThroughSerializer[T <: HasTileLinkData](gen: T, n: Int) extends Module { class FlowThroughSerializer[T <: Bundle with HasTileLinkData](gen: T, n: Int) extends Module {
val io = new Bundle { val io = new Bundle {
val in = Decoupled(gen).flip val in = Decoupled(gen).flip
val out = Decoupled(gen) val out = Decoupled(gen)
@ -96,7 +96,7 @@ class FlowThroughSerializer[T <: HasTileLinkData](gen: T, n: Int) extends Module
} }
object FlowThroughSerializer { object FlowThroughSerializer {
def apply[T <: HasTileLinkData](in: DecoupledIO[T], n: Int): DecoupledIO[T] = { def apply[T <: Bundle with HasTileLinkData](in: DecoupledIO[T], n: Int): DecoupledIO[T] = {
val fs = Module(new FlowThroughSerializer(in.bits, n)) val fs = Module(new FlowThroughSerializer(in.bits, n))
fs.io.in.valid := in.valid fs.io.in.valid := in.valid
fs.io.in.bits := in.bits fs.io.in.bits := in.bits