Removed all traces of params
This commit is contained in:
Henry Cook
@ -38,24 +38,25 @@ case object TLNetworkIsOrderedP2P extends Field[Boolean]
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case object TLWriteMaskBits extends Field[Int]
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/** Utility trait for building Modules and Bundles that use TileLink parameters */
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trait TileLinkParameters extends UsesParameters {
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val tlCoh = params(TLCoherencePolicy)
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val tlNManagers = params(TLNManagers)
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val tlNClients = params(TLNClients)
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val tlNCachingClients = params(TLNCachingClients)
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val tlNCachelessClients = params(TLNCachelessClients)
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trait HasTileLinkParameters {
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implicit val p: Parameters
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val tlCoh = p(TLCoherencePolicy)
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val tlNManagers = p(TLNManagers)
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val tlNClients = p(TLNClients)
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val tlNCachingClients = p(TLNCachingClients)
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val tlNCachelessClients = p(TLNCachelessClients)
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val tlClientIdBits = log2Up(tlNClients)
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val tlManagerIdBits = log2Up(tlNManagers)
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val tlMaxClientXacts = params(TLMaxClientXacts)
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val tlMaxClientsPerPort = params(TLMaxClientsPerPort)
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val tlMaxManagerXacts = params(TLMaxManagerXacts)
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val tlMaxClientXacts = p(TLMaxClientXacts)
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val tlMaxClientsPerPort = p(TLMaxClientsPerPort)
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val tlMaxManagerXacts = p(TLMaxManagerXacts)
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val tlClientXactIdBits = log2Up(tlMaxClientXacts*tlMaxClientsPerPort)
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val tlManagerXactIdBits = log2Up(tlMaxManagerXacts)
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val tlBlockAddrBits = params(TLBlockAddrBits)
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val tlDataBits = params(TLDataBits)
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val tlBlockAddrBits = p(TLBlockAddrBits)
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val tlDataBits = p(TLDataBits)
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val tlDataBytes = tlDataBits/8
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val tlDataBeats = params(TLDataBeats)
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val tlWriteMaskBits = params(TLWriteMaskBits)
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val tlDataBeats = p(TLDataBeats)
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val tlWriteMaskBits = p(TLWriteMaskBits)
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val tlBeatAddrBits = log2Up(tlDataBeats)
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val tlByteAddrBits = log2Up(tlWriteMaskBits)
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val tlMemoryOpcodeBits = M_SZ
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@ -68,32 +69,34 @@ trait TileLinkParameters extends UsesParameters {
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tlMemoryOpcodeBits)) + 1
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val tlGrantTypeBits = max(log2Up(Grant.nBuiltInTypes),
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tlCoh.grantTypeWidth) + 1
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val tlNetworkPreservesPointToPointOrdering = params(TLNetworkIsOrderedP2P)
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val tlNetworkPreservesPointToPointOrdering = p(TLNetworkIsOrderedP2P)
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val tlNetworkDoesNotInterleaveBeats = true
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val amoAluOperandBits = params(AmoAluOperandBits)
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val amoAluOperandBits = p(AmoAluOperandBits)
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}
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abstract class TLBundle extends Bundle with TileLinkParameters
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abstract class TLModule extends Module with TileLinkParameters
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abstract class TLModule(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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abstract class TLBundle(implicit val p: Parameters) extends junctions.ParameterizedBundle()(p)
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with HasTileLinkParameters
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/** Base trait for all TileLink channels */
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trait TileLinkChannel extends TLBundle {
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abstract class TileLinkChannel(implicit p: Parameters) extends TLBundle()(p) {
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def hasData(dummy: Int = 0): Bool
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def hasMultibeatData(dummy: Int = 0): Bool
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}
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/** Directionality of message channel. Used to hook up logical network ports to physical network ports */
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trait ClientToManagerChannel extends TileLinkChannel
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abstract class ClientToManagerChannel(implicit p: Parameters) extends TileLinkChannel()(p)
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/** Directionality of message channel. Used to hook up logical network ports to physical network ports */
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trait ManagerToClientChannel extends TileLinkChannel
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abstract class ManagerToClientChannel(implicit p: Parameters) extends TileLinkChannel()(p)
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/** Directionality of message channel. Used to hook up logical network ports to physical network ports */
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trait ClientToClientChannel extends TileLinkChannel // Unused for now
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abstract class ClientToClientChannel(implicit p: Parameters) extends TileLinkChannel()(p) // Unused for now
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/** Common signals that are used in multiple channels.
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* These traits are useful for type parameterizing bundle wiring functions.
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*/
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/** Address of a cache block. */
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trait HasCacheBlockAddress extends TLBundle {
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trait HasCacheBlockAddress extends HasTileLinkParameters {
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val addr_block = UInt(width = tlBlockAddrBits)
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def conflicts(that: HasCacheBlockAddress) = this.addr_block === that.addr_block
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@ -101,17 +104,17 @@ trait HasCacheBlockAddress extends TLBundle {
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}
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/** Sub-block address or beat id of multi-beat data */
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trait HasTileLinkBeatId extends TLBundle {
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trait HasTileLinkBeatId extends HasTileLinkParameters {
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val addr_beat = UInt(width = tlBeatAddrBits)
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}
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/* Client-side transaction id. Usually Miss Status Handling Register File index */
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trait HasClientTransactionId extends TLBundle {
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trait HasClientTransactionId extends HasTileLinkParameters {
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val client_xact_id = Bits(width = tlClientXactIdBits)
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}
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/** Manager-side transaction id. Usually Transaction Status Handling Register File index. */
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trait HasManagerTransactionId extends TLBundle {
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trait HasManagerTransactionId extends HasTileLinkParameters {
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val manager_xact_id = Bits(width = tlManagerXactIdBits)
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}
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@ -124,7 +127,7 @@ trait HasTileLinkData extends HasTileLinkBeatId {
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}
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/** The id of a client source or destination. Used in managers. */
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trait HasClientId extends TLBundle {
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trait HasClientId extends HasTileLinkParameters {
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val client_id = UInt(width = tlClientIdBits)
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}
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@ -138,7 +141,7 @@ trait HasClientId extends TLBundle {
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* PutAtomic built-in types. After sending an Acquire, clients must
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* wait for a manager to send them a [[uncore.Grant]] message in response.
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*/
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class Acquire extends ClientToManagerChannel
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class Acquire(implicit p: Parameters) extends ClientToManagerChannel()(p)
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with HasCacheBlockAddress
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with HasClientTransactionId
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with HasTileLinkData {
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@ -219,7 +222,7 @@ class Acquire extends ClientToManagerChannel
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}
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/** [[uncore.Acquire]] with an extra field stating its source id */
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class AcquireFromSrc extends Acquire with HasClientId
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class AcquireFromSrc(implicit p: Parameters) extends Acquire()(p) with HasClientId
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/** Contains definitions of the the built-in Acquire types and a factory
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* for [[uncore.Acquire]]
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@ -249,17 +252,18 @@ object Acquire {
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def typesWithMultibeatData = Vec(putBlockType)
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def typesOnSubBlocks = Vec(putType, getType, putAtomicType)
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def fullWriteMask = SInt(-1, width = new Acquire().tlWriteMaskBits).toUInt
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def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLWriteMaskBits)).toUInt
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// Most generic constructor
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def apply(
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is_builtin_type: Bool,
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a_type: Bits,
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0),
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union: UInt = UInt(0)): Acquire = {
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is_builtin_type: Bool,
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a_type: Bits,
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0),
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union: UInt = UInt(0))
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(implicit p: Parameters): Acquire = {
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val acq = Wire(new Acquire)
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acq.is_builtin_type := is_builtin_type
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acq.a_type := a_type
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@ -272,7 +276,7 @@ object Acquire {
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}
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// Copy constructor
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def apply(a: Acquire): Acquire = {
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val acq = Wire(new Acquire)
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val acq = Wire(new Acquire()(a.p))
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acq := a
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acq
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}
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@ -292,10 +296,11 @@ object Acquire {
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*/
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object Get {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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alloc: Bool = Bool(true)): Acquire = {
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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alloc: Bool = Bool(true))
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(implicit p: Parameters): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.getType,
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@ -305,12 +310,13 @@ object Get {
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union = Cat(MT_Q, M_XRD, alloc))
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}
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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addr_byte: UInt,
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operand_size: UInt,
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alloc: Bool): Acquire = {
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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addr_byte: UInt,
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operand_size: UInt,
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alloc: Bool)
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(implicit p: Parameters): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.getType,
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@ -332,9 +338,10 @@ object Get {
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*/
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object GetBlock {
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def apply(
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client_xact_id: UInt = UInt(0),
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addr_block: UInt,
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alloc: Bool = Bool(true)): Acquire = {
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client_xact_id: UInt = UInt(0),
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addr_block: UInt,
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alloc: Bool = Bool(true))
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(implicit p: Parameters): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.getBlockType,
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@ -352,8 +359,9 @@ object GetBlock {
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*/
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object GetPrefetch {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt): Acquire = {
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client_xact_id: UInt,
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addr_block: UInt)
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(implicit p: Parameters): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.prefetchType,
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@ -376,11 +384,12 @@ object GetPrefetch {
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*/
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object Put {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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data: UInt,
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wmask: UInt = Acquire.fullWriteMask): Acquire = {
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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data: UInt,
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wmask: Option[UInt]= None)
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(implicit p: Parameters): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.putType,
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@ -388,7 +397,7 @@ object Put {
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addr_beat = addr_beat,
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client_xact_id = client_xact_id,
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data = data,
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union = Cat(wmask, Bool(true)))
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union = Cat(wmask.getOrElse(Acquire.fullWriteMask), Bool(true)))
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}
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}
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@ -407,11 +416,12 @@ object Put {
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*/
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object PutBlock {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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data: UInt,
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wmask: UInt): Acquire = {
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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data: UInt,
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wmask: UInt)
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(implicit p: Parameters): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.putBlockType,
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@ -422,11 +432,12 @@ object PutBlock {
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union = Cat(wmask, (wmask != Acquire.fullWriteMask)))
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}
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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data: UInt,
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alloc: Bool = Bool(true)): Acquire = {
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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data: UInt,
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alloc: Bool = Bool(true))
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(implicit p: Parameters): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.putBlockType,
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@ -446,8 +457,9 @@ object PutBlock {
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*/
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object PutPrefetch {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt): Acquire = {
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client_xact_id: UInt,
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addr_block: UInt)
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(implicit p: Parameters): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.prefetchType,
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@ -470,13 +482,14 @@ object PutPrefetch {
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*/
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object PutAtomic {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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addr_byte: UInt,
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atomic_opcode: UInt,
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operand_size: UInt,
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data: UInt): Acquire = {
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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addr_byte: UInt,
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atomic_opcode: UInt,
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operand_size: UInt,
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data: UInt)
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(implicit p: Parameters): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.putAtomicType,
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@ -493,7 +506,7 @@ object PutAtomic {
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* The available types of Probes are customized by a particular
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* [[uncore.CoherencePolicy]].
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*/
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class Probe extends ManagerToClientChannel
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class Probe(implicit p: Parameters) extends ManagerToClientChannel()(p)
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with HasCacheBlockAddress {
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val p_type = UInt(width = tlCoh.probeTypeWidth)
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@ -503,7 +516,7 @@ class Probe extends ManagerToClientChannel
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}
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/** [[uncore.Probe]] with an extra field stating its destination id */
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class ProbeToDst extends Probe with HasClientId
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class ProbeToDst(implicit p: Parameters) extends Probe()(p) with HasClientId
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/** Contains factories for [[uncore.Probe]] and [[uncore.ProbeToDst]]
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*
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@ -515,13 +528,13 @@ class ProbeToDst extends Probe with HasClientId
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* @param addr_block address of the cache block
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*/
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object Probe {
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def apply(p_type: UInt, addr_block: UInt): Probe = {
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def apply(p_type: UInt, addr_block: UInt)(implicit p: Parameters): Probe = {
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val prb = Wire(new Probe)
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prb.p_type := p_type
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prb.addr_block := addr_block
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prb
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}
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def apply(dst: UInt, p_type: UInt, addr_block: UInt): ProbeToDst = {
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def apply(dst: UInt, p_type: UInt, addr_block: UInt)(implicit p: Parameters): ProbeToDst = {
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val prb = Wire(new ProbeToDst)
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prb.client_id := dst
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prb.p_type := p_type
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@ -537,7 +550,7 @@ object Probe {
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* a particular [[uncore.CoherencePolicy]]. Releases may contain data or may be
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* simple acknowledgements. Voluntary Releases are acknowledged with [[uncore.Grant Grants]].
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*/
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class Release extends ClientToManagerChannel
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class Release(implicit p: Parameters) extends ClientToManagerChannel()(p)
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with HasCacheBlockAddress
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with HasClientTransactionId
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with HasTileLinkData {
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@ -555,7 +568,7 @@ class Release extends ClientToManagerChannel
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}
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/** [[uncore.Release]] with an extra field stating its source id */
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class ReleaseFromSrc extends Release with HasClientId
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class ReleaseFromSrc(implicit p: Parameters) extends Release()(p) with HasClientId
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/** Contains a [[uncore.Release]] factory
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*
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@ -571,12 +584,13 @@ class ReleaseFromSrc extends Release with HasClientId
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*/
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object Release {
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def apply(
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voluntary: Bool,
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r_type: UInt,
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Release = {
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voluntary: Bool,
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r_type: UInt,
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0))
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(implicit p: Parameters): Release = {
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val rel = Wire(new Release)
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rel.r_type := r_type
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rel.client_xact_id := client_xact_id
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@ -595,7 +609,7 @@ object Release {
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* coherence policies may also define custom Grant types. Grants may contain data
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* or may be simple acknowledgements. Grants are responded to with [[uncore.Finish]].
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*/
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class Grant extends ManagerToClientChannel
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class Grant(implicit p: Parameters) extends ManagerToClientChannel()(p)
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with HasTileLinkData
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with HasClientTransactionId
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with HasManagerTransactionId {
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@ -616,14 +630,14 @@ class Grant extends ManagerToClientChannel
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def isVoluntary(dummy: Int = 0): Bool = isBuiltInType() && (g_type === Grant.voluntaryAckType)
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def requiresAck(dummy: Int = 0): Bool = !Bool(tlNetworkPreservesPointToPointOrdering) && !isVoluntary()
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def makeFinish(dummy: Int = 0): Finish = {
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val f = Wire(Bundle(new Finish, { case TLMaxManagerXacts => tlMaxManagerXacts }))
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val f = Wire(Bundle(new Finish))
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f.manager_xact_id := this.manager_xact_id
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f
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}
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}
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/** [[uncore.Grant]] with an extra field stating its destination */
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class GrantToDst extends Grant with HasClientId
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class GrantToDst(implicit p: Parameters) extends Grant()(p) with HasClientId
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/** Contains definitions of the the built-in grant types and factories
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* for [[uncore.Grant]] and [[uncore.GrantToDst]]
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@ -650,12 +664,13 @@ object Grant {
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def typesWithMultibeatData= Vec(getDataBlockType)
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def apply(
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is_builtin_type: Bool,
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||||
g_type: UInt,
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||||
client_xact_id: UInt,
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||||
manager_xact_id: UInt,
|
||||
addr_beat: UInt,
|
||||
data: UInt): Grant = {
|
||||
is_builtin_type: Bool,
|
||||
g_type: UInt,
|
||||
client_xact_id: UInt,
|
||||
manager_xact_id: UInt,
|
||||
addr_beat: UInt,
|
||||
data: UInt)
|
||||
(implicit p: Parameters): Grant = {
|
||||
val gnt = Wire(new Grant)
|
||||
gnt.is_builtin_type := is_builtin_type
|
||||
gnt.g_type := g_type
|
||||
@ -667,13 +682,14 @@ object Grant {
|
||||
}
|
||||
|
||||
def apply(
|
||||
dst: UInt,
|
||||
is_builtin_type: Bool,
|
||||
g_type: UInt,
|
||||
client_xact_id: UInt,
|
||||
manager_xact_id: UInt,
|
||||
addr_beat: UInt = UInt(0),
|
||||
data: UInt = UInt(0)): GrantToDst = {
|
||||
dst: UInt,
|
||||
is_builtin_type: Bool,
|
||||
g_type: UInt,
|
||||
client_xact_id: UInt,
|
||||
manager_xact_id: UInt,
|
||||
addr_beat: UInt = UInt(0),
|
||||
data: UInt = UInt(0))
|
||||
(implicit p: Parameters): GrantToDst = {
|
||||
val gnt = Wire(new GrantToDst)
|
||||
gnt.client_id := dst
|
||||
gnt.is_builtin_type := is_builtin_type
|
||||
@ -692,20 +708,21 @@ object Grant {
|
||||
* When a Finish message is received, a manager knows it is safe to begin
|
||||
* processing other transactions that touch the same cache block.
|
||||
*/
|
||||
class Finish extends ClientToManagerChannel with HasManagerTransactionId {
|
||||
class Finish(implicit p: Parameters) extends ClientToManagerChannel()(p)
|
||||
with HasManagerTransactionId {
|
||||
def hasData(dummy: Int = 0) = Bool(false)
|
||||
def hasMultibeatData(dummy: Int = 0) = Bool(false)
|
||||
}
|
||||
|
||||
/** Complete IO definition for incoherent TileLink, including networking headers */
|
||||
class UncachedTileLinkIO extends TLBundle {
|
||||
class UncachedTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
|
||||
val acquire = new DecoupledIO(new LogicalNetworkIO(new Acquire))
|
||||
val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
|
||||
val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
|
||||
}
|
||||
|
||||
/** Complete IO definition for coherent TileLink, including networking headers */
|
||||
class TileLinkIO extends UncachedTileLinkIO {
|
||||
class TileLinkIO(implicit p: Parameters) extends UncachedTileLinkIO()(p) {
|
||||
val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip
|
||||
val release = new DecoupledIO(new LogicalNetworkIO(new Release))
|
||||
}
|
||||
@ -722,7 +739,7 @@ class TileLinkIO extends UncachedTileLinkIO {
|
||||
* assumption that a [[uncore.FinishUnit]] has been coupled to the TileLinkIO port
|
||||
* to deal with acking received [[uncore.Grant Grants]].
|
||||
*/
|
||||
class ClientUncachedTileLinkIO extends TLBundle {
|
||||
class ClientUncachedTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
|
||||
val acquire = new DecoupledIO(new Acquire)
|
||||
val grant = new DecoupledIO(new Grant).flip
|
||||
}
|
||||
@ -730,7 +747,7 @@ class ClientUncachedTileLinkIO extends TLBundle {
|
||||
/** This version of TileLinkIO does not contain network headers.
|
||||
* It is intended for use within client agents.
|
||||
*/
|
||||
class ClientTileLinkIO extends ClientUncachedTileLinkIO {
|
||||
class ClientTileLinkIO(implicit p: Parameters) extends ClientUncachedTileLinkIO()(p) {
|
||||
val probe = new DecoupledIO(new Probe).flip
|
||||
val release = new DecoupledIO(new Release)
|
||||
}
|
||||
@ -749,7 +766,7 @@ class ClientTileLinkIO extends ClientUncachedTileLinkIO {
|
||||
* see Finished so they know when to allow new transactions on a cache
|
||||
* block to proceed.
|
||||
*/
|
||||
class ManagerTileLinkIO extends TLBundle {
|
||||
class ManagerTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
|
||||
val acquire = new DecoupledIO(new AcquireFromSrc).flip
|
||||
val grant = new DecoupledIO(new GrantToDst)
|
||||
val finish = new DecoupledIO(new Finish).flip
|
||||
@ -759,31 +776,21 @@ class ManagerTileLinkIO extends TLBundle {
|
||||
|
||||
/** Utilities for safely wrapping a *UncachedTileLink by pinning probe.ready and release.valid low */
|
||||
object TileLinkIOWrapper {
|
||||
def apply(utl: ClientUncachedTileLinkIO, p: Parameters): ClientTileLinkIO = {
|
||||
val conv = Module(new ClientTileLinkIOWrapper)(p)
|
||||
conv.io.in <> utl
|
||||
def apply(tl: ClientUncachedTileLinkIO)(implicit p: Parameters): ClientTileLinkIO = {
|
||||
val conv = Module(new ClientTileLinkIOWrapper)
|
||||
conv.io.in <> tl
|
||||
conv.io.out
|
||||
}
|
||||
def apply(utl: ClientUncachedTileLinkIO): ClientTileLinkIO = {
|
||||
val conv = Module(new ClientTileLinkIOWrapper)
|
||||
conv.io.in <> utl
|
||||
def apply(tl: UncachedTileLinkIO)(implicit p: Parameters): TileLinkIO = {
|
||||
val conv = Module(new TileLinkIOWrapper)
|
||||
conv.io.in <> tl
|
||||
conv.io.out
|
||||
}
|
||||
def apply(tl: ClientTileLinkIO): ClientTileLinkIO = tl
|
||||
def apply(utl: UncachedTileLinkIO, p: Parameters): TileLinkIO = {
|
||||
val conv = Module(new TileLinkIOWrapper)(p)
|
||||
conv.io.in <> utl
|
||||
conv.io.out
|
||||
}
|
||||
def apply(utl: UncachedTileLinkIO): TileLinkIO = {
|
||||
val conv = Module(new TileLinkIOWrapper)
|
||||
conv.io.in <> utl
|
||||
conv.io.out
|
||||
}
|
||||
def apply(tl: TileLinkIO): TileLinkIO = tl
|
||||
}
|
||||
|
||||
class TileLinkIOWrapper extends TLModule {
|
||||
class TileLinkIOWrapper(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = new UncachedTileLinkIO().flip
|
||||
val out = new TileLinkIO
|
||||
@ -795,7 +802,7 @@ class TileLinkIOWrapper extends TLModule {
|
||||
io.out.release.valid := Bool(false)
|
||||
}
|
||||
|
||||
class ClientTileLinkIOWrapper extends TLModule {
|
||||
class ClientTileLinkIOWrapper(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = new ClientUncachedTileLinkIO().flip
|
||||
val out = new ClientTileLinkIO
|
||||
@ -809,14 +816,16 @@ class ClientTileLinkIOWrapper extends TLModule {
|
||||
/** Used to track metadata for transactions where multiple secondary misses have been merged
|
||||
* and handled by a single transaction tracker.
|
||||
*/
|
||||
class SecondaryMissInfo extends TLBundle // TODO: add a_type to merge e.g. Get+GetBlocks, and/or HasClientId
|
||||
class SecondaryMissInfo(implicit p: Parameters) extends TLBundle()(p)
|
||||
with HasTileLinkBeatId
|
||||
with HasClientTransactionId
|
||||
// TODO: add a_type to merge e.g. Get+GetBlocks, and/or HasClientId
|
||||
|
||||
/** A helper module that automatically issues [[uncore.Finish]] messages in repsonse
|
||||
* to [[uncore.Grant]] that it receives from a manager and forwards to a client
|
||||
*/
|
||||
class FinishUnit(srcId: Int = 0, outstanding: Int = 2) extends TLModule with HasDataBeatCounters {
|
||||
class FinishUnit(srcId: Int = 0, outstanding: Int = 2)(implicit p: Parameters) extends TLModule()(p)
|
||||
with HasDataBeatCounters {
|
||||
val io = new Bundle {
|
||||
val grant = Decoupled(new LogicalNetworkIO(new Grant)).flip
|
||||
val refill = Decoupled(new Grant)
|
||||
@ -862,12 +871,12 @@ class FinishUnit(srcId: Int = 0, outstanding: Int = 2) extends TLModule with Has
|
||||
}
|
||||
}
|
||||
|
||||
class FinishQueueEntry extends TLBundle {
|
||||
class FinishQueueEntry(implicit p: Parameters) extends TLBundle()(p) {
|
||||
val fin = new Finish
|
||||
val dst = UInt(width = log2Up(params(LNEndpoints)))
|
||||
val dst = UInt(width = log2Up(p(LNEndpoints)))
|
||||
}
|
||||
|
||||
class FinishQueue(entries: Int) extends Queue(new FinishQueueEntry, entries)
|
||||
class FinishQueue(entries: Int)(implicit p: Parameters) extends Queue(new FinishQueueEntry()(p), entries)
|
||||
|
||||
/** A port to convert [[uncore.ClientTileLinkIO]].flip into [[uncore.TileLinkIO]]
|
||||
*
|
||||
@ -879,7 +888,8 @@ class FinishQueue(entries: Int) extends Queue(new FinishQueueEntry, entries)
|
||||
* @param clientId network port id of this agent
|
||||
* @param addrConvert how a physical address maps to a destination manager port id
|
||||
*/
|
||||
class ClientTileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt) extends TLModule {
|
||||
class ClientTileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt)
|
||||
(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val client = new ClientTileLinkIO().flip
|
||||
val network = new TileLinkIO
|
||||
@ -904,9 +914,10 @@ class ClientTileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt) extend
|
||||
|
||||
object ClientTileLinkHeaderCreator {
|
||||
def apply[T <: ClientToManagerChannel with HasCacheBlockAddress](
|
||||
in: DecoupledIO[T],
|
||||
clientId: Int,
|
||||
addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
in: DecoupledIO[T],
|
||||
clientId: Int,
|
||||
addrConvert: UInt => UInt)
|
||||
(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
|
||||
out.bits.payload := in.bits
|
||||
out.bits.header.src := UInt(clientId)
|
||||
@ -927,7 +938,8 @@ object ClientTileLinkHeaderCreator {
|
||||
* @param managerId the network port id of this agent
|
||||
* @param idConvert how a sharer id maps to a destination client port id
|
||||
*/
|
||||
class ManagerTileLinkNetworkPort(managerId: Int, idConvert: UInt => UInt) extends TLModule {
|
||||
class ManagerTileLinkNetworkPort(managerId: Int, idConvert: UInt => UInt)
|
||||
(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val manager = new ManagerTileLinkIO().flip
|
||||
val network = new TileLinkIO().flip
|
||||
@ -943,9 +955,10 @@ class ManagerTileLinkNetworkPort(managerId: Int, idConvert: UInt => UInt) extend
|
||||
|
||||
object ManagerTileLinkHeaderCreator {
|
||||
def apply[T <: ManagerToClientChannel with HasClientId](
|
||||
in: DecoupledIO[T],
|
||||
managerId: Int,
|
||||
idConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
in: DecoupledIO[T],
|
||||
managerId: Int,
|
||||
idConvert: UInt => UInt)
|
||||
(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
|
||||
out.bits.payload := in.bits
|
||||
out.bits.header.src := UInt(managerId)
|
||||
@ -960,7 +973,7 @@ object ManagerTileLinkHeaderCreator {
|
||||
case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int)
|
||||
|
||||
/** Optionally enqueues each [[uncore.TileLinkChannel]] individually */
|
||||
class TileLinkEnqueuer(depths: TileLinkDepths) extends Module {
|
||||
class TileLinkEnqueuer(depths: TileLinkDepths)(implicit p: Parameters) extends Module {
|
||||
val io = new Bundle {
|
||||
val client = new TileLinkIO().flip
|
||||
val manager = new TileLinkIO
|
||||
@ -973,18 +986,18 @@ class TileLinkEnqueuer(depths: TileLinkDepths) extends Module {
|
||||
}
|
||||
|
||||
object TileLinkEnqueuer {
|
||||
def apply(in: TileLinkIO, depths: TileLinkDepths)(p: Parameters): TileLinkIO = {
|
||||
val t = Module(new TileLinkEnqueuer(depths))(p)
|
||||
def apply(in: TileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): TileLinkIO = {
|
||||
val t = Module(new TileLinkEnqueuer(depths))
|
||||
t.io.client <> in
|
||||
t.io.manager
|
||||
}
|
||||
def apply(in: TileLinkIO, depth: Int)(p: Parameters): TileLinkIO = {
|
||||
apply(in, TileLinkDepths(depth, depth, depth, depth, depth))(p)
|
||||
def apply(in: TileLinkIO, depth: Int)(implicit p: Parameters): TileLinkIO = {
|
||||
apply(in, TileLinkDepths(depth, depth, depth, depth, depth))
|
||||
}
|
||||
}
|
||||
|
||||
/** Utility functions for constructing TileLinkIO arbiters */
|
||||
trait TileLinkArbiterLike extends TileLinkParameters {
|
||||
trait TileLinkArbiterLike extends HasTileLinkParameters {
|
||||
// Some shorthand type variables
|
||||
type ManagerSourcedWithId = ManagerToClientChannel with HasClientTransactionId
|
||||
type ClientSourcedWithId = ClientToManagerChannel with HasClientTransactionId
|
||||
@ -1086,7 +1099,8 @@ trait TileLinkArbiterLike extends TileLinkParameters {
|
||||
}
|
||||
|
||||
/** Abstract base case for any Arbiters that have UncachedTileLinkIOs */
|
||||
abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike {
|
||||
abstract class UncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module
|
||||
with TileLinkArbiterLike {
|
||||
val io = new Bundle {
|
||||
val in = Vec(new UncachedTileLinkIO, arbN).flip
|
||||
val out = new UncachedTileLinkIO
|
||||
@ -1097,7 +1111,8 @@ abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with Tile
|
||||
}
|
||||
|
||||
/** Abstract base case for any Arbiters that have cached TileLinkIOs */
|
||||
abstract class TileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike {
|
||||
abstract class TileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module
|
||||
with TileLinkArbiterLike {
|
||||
val io = new Bundle {
|
||||
val in = Vec(new TileLinkIO, arbN).flip
|
||||
val out = new TileLinkIO
|
||||
@ -1133,15 +1148,15 @@ trait UsesNewId extends TileLinkArbiterLike {
|
||||
}
|
||||
|
||||
// Now we can mix-in thevarious id-generation traits to make concrete arbiter classes
|
||||
class UncachedTileLinkIOArbiterThatAppendsArbiterId(val n: Int) extends UncachedTileLinkIOArbiter(n) with AppendsArbiterId
|
||||
class UncachedTileLinkIOArbiterThatPassesId(val n: Int) extends UncachedTileLinkIOArbiter(n) with PassesId
|
||||
class UncachedTileLinkIOArbiterThatUsesNewId(val n: Int) extends UncachedTileLinkIOArbiter(n) with UsesNewId
|
||||
class TileLinkIOArbiterThatAppendsArbiterId(val n: Int) extends TileLinkIOArbiter(n) with AppendsArbiterId
|
||||
class TileLinkIOArbiterThatPassesId(val n: Int) extends TileLinkIOArbiter(n) with PassesId
|
||||
class TileLinkIOArbiterThatUsesNewId(val n: Int) extends TileLinkIOArbiter(n) with UsesNewId
|
||||
class UncachedTileLinkIOArbiterThatAppendsArbiterId(val n: Int)(implicit p: Parameters) extends UncachedTileLinkIOArbiter(n)(p) with AppendsArbiterId
|
||||
class UncachedTileLinkIOArbiterThatPassesId(val n: Int)(implicit p: Parameters) extends UncachedTileLinkIOArbiter(n)(p) with PassesId
|
||||
class UncachedTileLinkIOArbiterThatUsesNewId(val n: Int)(implicit p: Parameters) extends UncachedTileLinkIOArbiter(n)(p) with UsesNewId
|
||||
class TileLinkIOArbiterThatAppendsArbiterId(val n: Int)(implicit p: Parameters) extends TileLinkIOArbiter(n)(p) with AppendsArbiterId
|
||||
class TileLinkIOArbiterThatPassesId(val n: Int)(implicit p: Parameters) extends TileLinkIOArbiter(n)(p) with PassesId
|
||||
class TileLinkIOArbiterThatUsesNewId(val n: Int)(implicit p: Parameters) extends TileLinkIOArbiter(n)(p) with UsesNewId
|
||||
|
||||
/** Concrete uncached client-side arbiter that appends the arbiter's port id to client_xact_id */
|
||||
class ClientUncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId {
|
||||
class ClientUncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module with TileLinkArbiterLike with AppendsArbiterId {
|
||||
val io = new Bundle {
|
||||
val in = Vec(new ClientUncachedTileLinkIO, arbN).flip
|
||||
val out = new ClientUncachedTileLinkIO
|
||||
@ -1151,7 +1166,7 @@ class ClientUncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLin
|
||||
}
|
||||
|
||||
/** Concrete client-side arbiter that appends the arbiter's port id to client_xact_id */
|
||||
class ClientTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId {
|
||||
class ClientTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module with TileLinkArbiterLike with AppendsArbiterId {
|
||||
val io = new Bundle {
|
||||
val in = Vec(new ClientTileLinkIO, arbN).flip
|
||||
val out = new ClientTileLinkIO
|
||||
@ -1246,7 +1261,7 @@ class ClientTileLinkIOUnwrapperInfo extends Bundle {
|
||||
val builtin = Bool()
|
||||
}
|
||||
|
||||
class ClientTileLinkIOUnwrapper extends TLModule {
|
||||
class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = new ClientTileLinkIO().flip
|
||||
val out = new ClientUncachedTileLinkIO
|
||||
@ -1328,12 +1343,13 @@ class ClientTileLinkIOUnwrapper extends TLModule {
|
||||
io.in.probe.valid := Bool(false)
|
||||
}
|
||||
|
||||
class NastiIOTileLinkIOConverterInfo extends TLBundle {
|
||||
class NastiIOTileLinkIOConverterInfo(implicit p: Parameters) extends TLBundle()(p) {
|
||||
val byteOff = UInt(width = tlByteAddrBits)
|
||||
val subblock = Bool()
|
||||
}
|
||||
|
||||
class NastiIOTileLinkIOConverter(implicit val p: Parameters) extends TLModule with HasNastiParameters {
|
||||
class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
|
||||
with HasNastiParameters {
|
||||
val io = new Bundle {
|
||||
val tl = new ClientUncachedTileLinkIO().flip
|
||||
val nasti = new NastiIO
|
||||
@ -1349,7 +1365,7 @@ class NastiIOTileLinkIOConverter(implicit val p: Parameters) extends TLModule wi
|
||||
MT_Q -> UInt(log2Up(tlDataBytes))))
|
||||
|
||||
val dataBits = tlDataBits*tlDataBeats
|
||||
val dstIdBits = params(LNHeaderBits)
|
||||
val dstIdBits = p(LNHeaderBits)
|
||||
require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
|
||||
require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
|
||||
require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NastiIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits)
|
||||
|
||||
Reference in New Issue
Block a user