riscv/rocket-chip
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Removed all traces of params

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This commit is contained in:
Henry Cook
2015-10-05 21:41:46 -07:00
parent 908922c1a4
commit 31be6407ec
11 changed files with 456 additions and 425 deletions
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14
uncore/src/main/scala/scr.scala
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@@ -3,24 +3,24 @@ package uncore
import Chisel._
import junctions.{SMIIO, MMIOBase}
class SCRIO extends HTIFBundle {
val rdata = Vec(Bits(INPUT, 64), nSCR)
class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
val rdata = Vec(Bits(INPUT, scrDataBits), nSCR)
val wen = Bool(OUTPUT)
val waddr = UInt(OUTPUT, log2Up(nSCR))
val wdata = Bits(OUTPUT, 64)
val wdata = Bits(OUTPUT, scrDataBits)
}
class SCRFile extends Module with HTIFParameters {
class SCRFile(implicit p: Parameters) extends HtifModule()(p) {
val io = new Bundle {
val smi = new SMIIO(64, scrAddrBits).flip
val smi = new SMIIO(scrDataBits, scrAddrBits).flip
val scr = new SCRIO
}
val scr_rdata = Wire(Vec(Bits(width=64), io.scr.rdata.size))
val scr_rdata = Wire(Vec(Bits(width=scrDataBits), io.scr.rdata.size))
for (i <- 0 until scr_rdata.size)
scr_rdata(i) := io.scr.rdata(i)
scr_rdata(0) := UInt(nCores)
scr_rdata(1) := UInt(params(MMIOBase) >> 20)
scr_rdata(1) := UInt(p(MMIOBase) >> 20)
val read_addr = Reg(init = UInt(0, scrAddrBits))
val resp_valid = Reg(init = Bool(false))