Removed all traces of params
This commit is contained in:
Henry Cook
@ -18,23 +18,26 @@ case object CacheBlockBytes extends Field[Int]
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case object CacheBlockOffsetBits extends Field[Int]
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case object ECCCode extends Field[Option[Code]]
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abstract trait CacheParameters extends UsesParameters {
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val nSets = params(NSets)
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val blockOffBits = params(CacheBlockOffsetBits)
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trait HasCacheParameters {
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implicit val p: Parameters
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val nSets = p(NSets)
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val blockOffBits = p(CacheBlockOffsetBits)
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val idxBits = log2Up(nSets)
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val untagBits = blockOffBits + idxBits
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val tagBits = params(PAddrBits) - untagBits
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val nWays = params(NWays)
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val tagBits = p(PAddrBits) - untagBits
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val nWays = p(NWays)
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val wayBits = log2Up(nWays)
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val isDM = nWays == 1
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val rowBits = params(RowBits)
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val rowBits = p(RowBits)
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val rowBytes = rowBits/8
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val rowOffBits = log2Up(rowBytes)
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val code = params(ECCCode).getOrElse(new IdentityCode)
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val code = p(ECCCode).getOrElse(new IdentityCode)
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}
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abstract class CacheBundle extends Bundle with CacheParameters
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abstract class CacheModule extends Module with CacheParameters
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abstract class CacheModule(implicit val p: Parameters) extends Module
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with HasCacheParameters
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abstract class CacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasCacheParameters
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class StoreGen(typ: UInt, addr: UInt, dat: UInt) {
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val byte = typ === MT_B || typ === MT_BU
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@ -66,8 +69,8 @@ class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool) {
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val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
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}
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class AMOALU extends CacheModule {
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val operandBits = params(AmoAluOperandBits)
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class AMOALU(implicit p: Parameters) extends CacheModule()(p) {
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val operandBits = p(AmoAluOperandBits)
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require(operandBits == 64)
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val io = new Bundle {
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val addr = Bits(INPUT, blockOffBits)
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@ -125,23 +128,23 @@ class RandomReplacement(ways: Int) extends ReplacementPolicy {
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def hit = {}
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}
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abstract class Metadata extends CacheBundle {
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abstract class Metadata(implicit p: Parameters) extends CacheBundle()(p) {
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val tag = Bits(width = tagBits)
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val coh: CoherenceMetadata
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}
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class MetaReadReq extends CacheBundle {
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class MetaReadReq(implicit p: Parameters) extends CacheBundle()(p) {
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val idx = Bits(width = idxBits)
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}
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class MetaWriteReq[T <: Metadata](gen: T) extends MetaReadReq {
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class MetaWriteReq[T <: Metadata](gen: T)(implicit p: Parameters) extends MetaReadReq()(p) {
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val way_en = Bits(width = nWays)
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val data = gen.cloneType
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override def cloneType = new MetaWriteReq(gen).asInstanceOf[this.type]
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override def cloneType = new MetaWriteReq(gen)(p).asInstanceOf[this.type]
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}
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class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
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val rstVal = makeRstVal()
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class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) extends CacheModule()(p) {
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val rstVal = onReset()
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val io = new Bundle {
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val read = Decoupled(new MetaReadReq).flip
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val write = Decoupled(new MetaWriteReq(rstVal)).flip
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@ -166,24 +169,24 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
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io.write.ready := !rst
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}
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abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgentParameters {
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trait HasL2HellaCacheParameters extends HasCacheParameters with HasCoherenceAgentParameters {
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val idxMSB = idxBits-1
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val idxLSB = 0
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val blockAddrBits = params(TLBlockAddrBits)
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val blockAddrBits = p(TLBlockAddrBits)
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val refillCyclesPerBeat = outerDataBits/rowBits
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val refillCycles = refillCyclesPerBeat*outerDataBeats
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val internalDataBeats = params(CacheBlockBytes)*8/rowBits
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val internalDataBeats = p(CacheBlockBytes)*8/rowBits
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require(refillCyclesPerBeat == 1)
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val amoAluOperandBits = params(AmoAluOperandBits)
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val amoAluOperandBits = p(AmoAluOperandBits)
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require(amoAluOperandBits <= innerDataBits)
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require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states
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val nSecondaryMisses = params(NSecondaryMisses)
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val nSecondaryMisses = p(NSecondaryMisses)
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val isLastLevelCache = true
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val ignoresWriteMask = !params(ECCCode).isEmpty
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val ignoresWriteMask = !p(ECCCode).isEmpty
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}
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abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
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abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters {
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abstract class L2HellaCacheModule(implicit val p: Parameters) extends Module
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with HasL2HellaCacheParameters {
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def doInternalOutputArbitration[T <: Data : ClassTag](
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out: DecoupledIO[T],
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ins: Seq[DecoupledIO[T]]) {
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@ -192,39 +195,42 @@ abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters {
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arb.io.in <> ins
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}
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def doInternalInputRouting[T <: HasL2Id](in: ValidIO[T], outs: Seq[ValidIO[T]]) {
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def doInternalInputRouting[T <: Bundle with HasL2Id](in: ValidIO[T], outs: Seq[ValidIO[T]]) {
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outs.map(_.bits := in.bits)
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outs.zipWithIndex.map { case (o,i) => o.valid := in.valid && in.bits.id === UInt(i) }
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}
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}
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trait HasL2Id extends Bundle with CoherenceAgentParameters {
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abstract class L2HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasL2HellaCacheParameters
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trait HasL2Id extends HasCoherenceAgentParameters {
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val id = UInt(width = log2Up(nTransactors + 1))
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}
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trait HasL2InternalRequestState extends L2HellaCacheBundle {
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trait HasL2InternalRequestState extends HasL2HellaCacheParameters {
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val tag_match = Bool()
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val meta = new L2Metadata
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val way_en = Bits(width = nWays)
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}
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trait HasL2BeatAddr extends L2HellaCacheBundle {
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trait HasL2BeatAddr extends HasL2HellaCacheParameters {
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val addr_beat = UInt(width = log2Up(refillCycles))
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}
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trait HasL2Data extends L2HellaCacheBundle
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trait HasL2Data extends HasL2HellaCacheParameters
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with HasL2BeatAddr {
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val data = UInt(width = rowBits)
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def hasData(dummy: Int = 0) = Bool(true)
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def hasMultibeatData(dummy: Int = 0) = Bool(refillCycles > 1)
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}
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class L2Metadata extends Metadata with L2HellaCacheParameters {
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class L2Metadata(implicit p: Parameters) extends Metadata()(p) with HasL2HellaCacheParameters {
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val coh = new HierarchicalMetadata
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}
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object L2Metadata {
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def apply(tag: Bits, coh: HierarchicalMetadata) = {
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def apply(tag: Bits, coh: HierarchicalMetadata)(implicit p: Parameters) = {
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val meta = Wire(new L2Metadata)
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meta.tag := tag
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meta.coh := coh
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@ -232,31 +238,33 @@ object L2Metadata {
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}
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}
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class L2MetaReadReq extends MetaReadReq with HasL2Id {
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class L2MetaReadReq(implicit p: Parameters) extends MetaReadReq()(p) with HasL2Id {
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val tag = Bits(width = tagBits)
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}
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class L2MetaWriteReq extends MetaWriteReq[L2Metadata](new L2Metadata)
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class L2MetaWriteReq(implicit p: Parameters) extends MetaWriteReq[L2Metadata](new L2Metadata)(p)
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with HasL2Id {
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override def cloneType = new L2MetaWriteReq().asInstanceOf[this.type]
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}
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class L2MetaResp extends L2HellaCacheBundle
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class L2MetaResp(implicit p: Parameters) extends L2HellaCacheBundle()(p)
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with HasL2Id
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with HasL2InternalRequestState
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trait HasL2MetaReadIO extends L2HellaCacheBundle {
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trait HasL2MetaReadIO extends HasL2HellaCacheParameters {
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val read = Decoupled(new L2MetaReadReq)
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val resp = Valid(new L2MetaResp).flip
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}
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trait HasL2MetaWriteIO extends L2HellaCacheBundle {
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trait HasL2MetaWriteIO extends HasL2HellaCacheParameters {
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val write = Decoupled(new L2MetaWriteReq)
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}
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class L2MetaRWIO extends L2HellaCacheBundle with HasL2MetaReadIO with HasL2MetaWriteIO
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class L2MetaRWIO(implicit p: Parameters) extends L2HellaCacheBundle()(p)
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with HasL2MetaReadIO
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with HasL2MetaWriteIO
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class L2MetadataArray extends L2HellaCacheModule {
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class L2MetadataArray(implicit p: Parameters) extends L2HellaCacheModule()(p) {
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val io = new L2MetaRWIO().flip
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def onReset = L2Metadata(UInt(0), HierarchicalMetadata.onReset)
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@ -274,7 +282,7 @@ class L2MetadataArray extends L2HellaCacheModule {
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val s2_tag_match = s2_tag_match_way.orR
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val s2_hit_coh = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
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val replacer = params(Replacer)()
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val replacer = p(Replacer)()
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val s1_replaced_way_en = UIntToOH(replacer.way)
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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@ -290,32 +298,36 @@ class L2MetadataArray extends L2HellaCacheModule {
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io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
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}
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class L2DataReadReq extends L2HellaCacheBundle
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class L2DataReadReq(implicit p: Parameters) extends L2HellaCacheBundle()(p)
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with HasL2BeatAddr
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with HasL2Id {
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val addr_idx = UInt(width = idxBits)
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val way_en = Bits(width = nWays)
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}
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class L2DataWriteReq extends L2DataReadReq
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class L2DataWriteReq(implicit p: Parameters) extends L2DataReadReq()(p)
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with HasL2Data {
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val wmask = Bits(width = rowBits/8)
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}
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class L2DataResp extends L2HellaCacheBundle with HasL2Id with HasL2Data
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class L2DataResp(implicit p: Parameters) extends L2HellaCacheBundle()(p)
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with HasL2Id
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with HasL2Data
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trait HasL2DataReadIO extends L2HellaCacheBundle {
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trait HasL2DataReadIO extends HasL2HellaCacheParameters {
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val read = Decoupled(new L2DataReadReq)
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val resp = Valid(new L2DataResp).flip
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}
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trait HasL2DataWriteIO extends L2HellaCacheBundle {
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trait HasL2DataWriteIO extends HasL2HellaCacheParameters {
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val write = Decoupled(new L2DataWriteReq)
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}
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class L2DataRWIO extends L2HellaCacheBundle with HasL2DataReadIO with HasL2DataWriteIO
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class L2DataRWIO(implicit p: Parameters) extends L2HellaCacheBundle()(p)
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with HasL2DataReadIO
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with HasL2DataWriteIO
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class L2DataArray(delay: Int) extends L2HellaCacheModule {
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class L2DataArray(delay: Int)(implicit p: Parameters) extends L2HellaCacheModule()(p) {
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val io = new L2DataRWIO().flip
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val array = SeqMem(Vec(Bits(width=8), rowBits/8), nWays*nSets*refillCycles)
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@ -333,7 +345,8 @@ class L2DataArray(delay: Int) extends L2HellaCacheModule {
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io.write.ready := Bool(true)
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}
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class L2HellaCacheBank extends HierarchicalCoherenceAgent with L2HellaCacheParameters {
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class L2HellaCacheBank(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p)
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with HasL2HellaCacheParameters {
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require(isPow2(nSets))
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require(isPow2(nWays))
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@ -347,12 +360,13 @@ class L2HellaCacheBank extends HierarchicalCoherenceAgent with L2HellaCacheParam
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data.io <> tshrfile.io.data
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}
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class TSHRFileIO extends HierarchicalTLIO {
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class TSHRFileIO(implicit p: Parameters) extends HierarchicalTLIO()(p) {
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val meta = new L2MetaRWIO
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val data = new L2DataRWIO
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}
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class TSHRFile extends L2HellaCacheModule with HasCoherenceAgentWiringHelpers {
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class TSHRFile(implicit p: Parameters) extends L2HellaCacheModule()(p)
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with HasCoherenceAgentWiringHelpers {
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val io = new TSHRFileIO
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// Create TSHRs for outstanding transactions
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@ -418,15 +432,16 @@ class TSHRFile extends L2HellaCacheModule with HasCoherenceAgentWiringHelpers {
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}
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class L2XactTrackerIO extends HierarchicalXactTrackerIO {
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class L2XactTrackerIO(implicit p: Parameters) extends HierarchicalXactTrackerIO()(p) {
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val data = new L2DataRWIO
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val meta = new L2MetaRWIO
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val wb = new L2WritebackIO
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}
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abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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abstract class L2XactTracker(implicit p: Parameters) extends XactTracker()(p)
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with HasL2HellaCacheParameters {
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class CacheBlockBuffer { // TODO
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val buffer = Reg(Bits(width = params(CacheBlockBytes)*8))
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val buffer = Reg(Bits(width = p(CacheBlockBytes)*8))
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def internal = Vec(Bits(width = rowBits), internalDataBeats).fromBits(buffer)
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def inner = Vec(Bits(width = innerDataBits), innerDataBeats).fromBits(buffer)
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@ -440,29 +455,29 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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} else { (UInt(0), inc) }
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}
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def connectInternalDataBeatCounter[T <: HasL2BeatAddr](
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def connectInternalDataBeatCounter[T <: L2HellaCacheBundle with HasL2BeatAddr](
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in: DecoupledIO[T],
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beat: UInt = UInt(0),
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full_block: Bool = Bool(true)): (UInt, Bool) = {
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connectDataBeatCounter(in.fire(), in.bits, beat, full_block)
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}
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def connectInternalDataBeatCounter[T <: HasL2Data](
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def connectInternalDataBeatCounter[T <: L2HellaCacheBundle with HasL2Data](
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in: ValidIO[T],
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full_block: Bool): Bool = {
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connectDataBeatCounter(in.valid, in.bits, UInt(0), full_block)._2
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}
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def addPendingBitInternal[T <: HasL2BeatAddr](in: DecoupledIO[T]) =
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def addPendingBitInternal[T <: L2HellaCacheBundle with HasL2BeatAddr](in: DecoupledIO[T]) =
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Fill(in.bits.refillCycles, in.fire()) & UIntToOH(in.bits.addr_beat)
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def addPendingBitInternal[T <: HasL2BeatAddr](in: ValidIO[T]) =
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def addPendingBitInternal[T <: L2HellaCacheBundle with HasL2BeatAddr](in: ValidIO[T]) =
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Fill(in.bits.refillCycles, in.valid) & UIntToOH(in.bits.addr_beat)
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def dropPendingBit[T <: HasL2BeatAddr] (in: DecoupledIO[T]) =
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def dropPendingBit[T <: L2HellaCacheBundle with HasL2BeatAddr] (in: DecoupledIO[T]) =
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~Fill(in.bits.refillCycles, in.fire()) | ~UIntToOH(in.bits.addr_beat)
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def dropPendingBitInternal[T <: HasL2BeatAddr] (in: ValidIO[T]) =
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def dropPendingBitInternal[T <: L2HellaCacheBundle with HasL2BeatAddr] (in: ValidIO[T]) =
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~Fill(in.bits.refillCycles, in.valid) | ~UIntToOH(in.bits.addr_beat)
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def addPendingBitWhenBeatHasPartialWritemask(in: DecoupledIO[AcquireFromSrc]): UInt = {
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@ -474,10 +489,10 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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def pinAllReadyValidLow[T <: Data](b: Bundle) {
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b.elements.foreach {
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_._2 match {
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case d: DecoupledIO[T] =>
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case d: DecoupledIO[_] =>
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if(d.ready.dir == OUTPUT) d.ready := Bool(false)
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else if(d.valid.dir == OUTPUT) d.valid := Bool(false)
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case v: ValidIO[T] => if(v.valid.dir == OUTPUT) v.valid := Bool(false)
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case v: ValidIO[_] => if(v.valid.dir == OUTPUT) v.valid := Bool(false)
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case b: Bundle => pinAllReadyValidLow(b)
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case _ =>
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}
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@ -485,14 +500,14 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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}
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}
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class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
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class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTracker()(p) {
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val io = new L2XactTrackerIO
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pinAllReadyValidLow(io)
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val s_idle :: s_meta_read :: s_meta_resp :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 5)
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val state = Reg(init=s_idle)
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val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
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val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => p(InnerTLId); case TLDataBits => 0 }))
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val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
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val xact_way_en = Reg{ Bits(width = nWays) }
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val xact_old_meta = Reg{ new L2Metadata }
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@ -579,7 +594,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
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}
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class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTracker()(p) {
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val io = new L2XactTrackerIO
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pinAllReadyValidLow(io)
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@ -587,7 +602,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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val state = Reg(init=s_idle)
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// State holding transaction metadata
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val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) }))
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val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => p(InnerTLId) }))
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val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
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val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8)))
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val xact_tag_match = Reg{ Bool() }
|
||||
@ -667,15 +682,15 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
|
||||
wmask_buffer(beat) := ~UInt(0, wmask_buffer.head.getWidth)
|
||||
when(xact.is(Acquire.putAtomicType) && xact.addr_beat === beat) { amo_result := old_data }
|
||||
}
|
||||
def mergeDataInternal[T <: HasL2Data with HasL2BeatAddr](in: ValidIO[T]) {
|
||||
def mergeDataInternal[T <: L2HellaCacheBundle with HasL2Data with HasL2BeatAddr](in: ValidIO[T]) {
|
||||
when(in.valid) { mergeData(rowBits)(in.bits.addr_beat, in.bits.data) }
|
||||
}
|
||||
def mergeDataInner[T <: HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[T]) {
|
||||
def mergeDataInner[T <: TLBundle with HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[T]) {
|
||||
when(in.fire() && in.bits.hasData()) {
|
||||
mergeData(innerDataBits)(in.bits.addr_beat, in.bits.data)
|
||||
}
|
||||
}
|
||||
def mergeDataOuter[T <: HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[T]) {
|
||||
def mergeDataOuter[T <: TLBundle with HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[T]) {
|
||||
when(in.fire() && in.bits.hasData()) {
|
||||
mergeData(outerDataBits)(in.bits.addr_beat, in.bits.data)
|
||||
}
|
||||
@ -956,24 +971,24 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
|
||||
"AcquireTracker accepted data beat from different network source than initial request.")
|
||||
}
|
||||
|
||||
class L2WritebackReq extends L2Metadata with HasL2Id {
|
||||
class L2WritebackReq(implicit p: Parameters) extends L2Metadata()(p) with HasL2Id {
|
||||
val idx = Bits(width = idxBits)
|
||||
val way_en = Bits(width = nWays)
|
||||
}
|
||||
|
||||
class L2WritebackResp extends L2HellaCacheBundle with HasL2Id
|
||||
class L2WritebackResp(implicit p: Parameters) extends L2HellaCacheBundle()(p) with HasL2Id
|
||||
|
||||
class L2WritebackIO extends L2HellaCacheBundle {
|
||||
class L2WritebackIO(implicit p: Parameters) extends L2HellaCacheBundle()(p) {
|
||||
val req = Decoupled(new L2WritebackReq)
|
||||
val resp = Valid(new L2WritebackResp).flip
|
||||
}
|
||||
|
||||
class L2WritebackUnitIO extends HierarchicalXactTrackerIO {
|
||||
class L2WritebackUnitIO(implicit p: Parameters) extends HierarchicalXactTrackerIO()(p) {
|
||||
val wb = new L2WritebackIO().flip
|
||||
val data = new L2DataRWIO
|
||||
}
|
||||
|
||||
class L2WritebackUnit(trackerId: Int) extends L2XactTracker {
|
||||
class L2WritebackUnit(trackerId: Int)(implicit p: Parameters) extends L2XactTracker()(p) {
|
||||
val io = new L2WritebackUnitIO
|
||||
pinAllReadyValidLow(io)
|
||||
|
||||
|
||||
Reference in New Issue
Block a user