riscv/rocket-chip
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Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.

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This commit is contained in:
Stephen Twigg 2013-07-30 16:36:28 -07:00
parent 9abdf4e154
commit 3132db4f90
1 changed files with 7 additions and 1 deletions
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8
rocket/src/main/scala/dpath_util.scala
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@ -97,6 +97,7 @@ object PCR
val K1 = 13 val K1 = 13
val VECBANK = 18 val VECBANK = 18
val VECCFG = 19 val VECCFG = 19
val STATS = 28
val RESET = 29 val RESET = 29
val TOHOST = 30 val TOHOST = 30
val FROMHOST = 31 val FROMHOST = 31
@ -131,6 +132,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
val replay = Bool(OUTPUT) val replay = Bool(OUTPUT)
val vecbank = Bits(OUTPUT, 8) val vecbank = Bits(OUTPUT, 8)
val vecbankcnt = UFix(OUTPUT, 4) val vecbankcnt = UFix(OUTPUT, 4)
val stats = Bool(OUTPUT)
val vec_appvl = UFix(INPUT, 12) val vec_appvl = UFix(INPUT, 12)
val vec_nxregs = UFix(INPUT, 6) val vec_nxregs = UFix(INPUT, 6)
val vec_nfregs = UFix(INPUT, 6) val vec_nfregs = UFix(INPUT, 6)
@ -150,6 +152,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
val reg_k1 = Reg{Bits(width = conf.xprlen)} val reg_k1 = Reg{Bits(width = conf.xprlen)}
val reg_ptbr = Reg{UFix(width = PADDR_BITS)} val reg_ptbr = Reg{UFix(width = PADDR_BITS)}
val reg_vecbank = Reg(resetVal = Fix(-1,8).toBits) val reg_vecbank = Reg(resetVal = Fix(-1,8).toBits)
val reg_stats = Reg(resetVal = Bool(false))
val reg_error_mode = Reg(resetVal = Bool(false)) val reg_error_mode = Reg(resetVal = Bool(false))
val reg_status = Reg{new Status} // reset down below val reg_status = Reg{new Status} // reset down below
@ -193,6 +196,8 @@ class PCR(implicit conf: RocketConfiguration) extends Component
cnt = cnt + reg_vecbank(i) cnt = cnt + reg_vecbank(i)
io.vecbankcnt := cnt(3,0) io.vecbankcnt := cnt(3,0)
io.stats := reg_stats
when (io.badvaddr_wen || io.vec_irq_aux_wen) { when (io.badvaddr_wen || io.vec_irq_aux_wen) {
val wdata = Mux(io.badvaddr_wen, io.rw.wdata, io.vec_irq_aux) val wdata = Mux(io.badvaddr_wen, io.rw.wdata, io.vec_irq_aux)
val (upper, lower) = Split(wdata, VADDR_BITS) val (upper, lower) = Split(wdata, VADDR_BITS)
@ -240,7 +245,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank, read_veccfg, reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank, read_veccfg,
reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/,
reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/,
reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost, reg_fromhost reg_stats/*x*/, read_veccfg/*x*/, reg_tohost, reg_fromhost
)(addr) )(addr)
when (wen) { when (wen) {
@ -267,6 +272,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
when (addr === K1) { reg_k1 := wdata; } when (addr === K1) { reg_k1 := wdata; }
when (addr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; } when (addr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (addr === VECBANK) { reg_vecbank:= wdata(7,0) } when (addr === VECBANK) { reg_vecbank:= wdata(7,0) }
when (addr === STATS) { reg_stats := wdata(0) }
} }
io.host.ipi_rep.ready := Bool(true) io.host.ipi_rep.ready := Bool(true)