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subsystem: add some inter-wrapper buffer params

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This commit is contained in:
Henry Cook 2018-02-23 14:50:39 -08:00
parent ad823ef43c
commit 30c0635bb3
4 changed files with 20 additions and 12 deletions
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4
src/main/scala/subsystem/BaseSubsystem.scala
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@ -37,11 +37,11 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem {
val fbus = LazyModule(new FrontBus(p(FrontBusKey))) val fbus = LazyModule(new FrontBus(p(FrontBusKey)))
// The sbus masters the pbus; here we convert TL-UH -> TL-UL // The sbus masters the pbus; here we convert TL-UH -> TL-UL
pbus.fromSystemBus() { sbus.toPeripheryBus() { pbus.crossTLIn } } pbus.fromSystemBus { sbus.toPeripheryBus { pbus.crossTLIn } }
// The fbus masters the sbus; both are TL-UH or TL-C // The fbus masters the sbus; both are TL-UH or TL-C
FlipRendering { implicit p => FlipRendering { implicit p =>
fbus.toSystemBus() { sbus.fromFrontBus { fbus.crossTLOut } } fbus.toSystemBus { sbus.fromFrontBus { fbus.crossTLOut } }
} }
// The sbus masters the mbus; here we convert TL-C -> TL-UH // The sbus masters the mbus; here we convert TL-C -> TL-UH

13
src/main/scala/subsystem/FrontBus.scala
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@ -8,14 +8,19 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
case class FrontBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusParams case class FrontBusParams(
beatBytes: Int,
blockBytes: Int,
sbusCrossing: SubsystemClockCrossing = SynchronousCrossing(),
sbusBuffer: BufferParams = BufferParams.default) extends HasTLBusParams
case object FrontBusKey extends Field[FrontBusParams] case object FrontBusKey extends Field[FrontBusParams]
class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = SynchronousCrossing()) class FrontBus(params: FrontBusParams)
(implicit p: Parameters) extends TLBusWrapper(params, "front_bus") (implicit p: Parameters) extends TLBusWrapper(params, "front_bus")
with HasTLXbarPhy with HasTLXbarPhy
with HasCrossing { with HasCrossing {
val crossing = params.sbusCrossing
def fromPort[D,U,E,B <: Data] def fromPort[D,U,E,B <: Data]
(name: Option[String] = None, buffers: Int = 1) (name: Option[String] = None, buffers: Int = 1)
@ -39,7 +44,7 @@ class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = Sy
from("coherent_subsystem") { inwardNode :=* gen } from("coherent_subsystem") { inwardNode :=* gen }
} }
def toSystemBus(buffer: BufferParams = BufferParams.none)(gen: => TLInwardNode) { def toSystemBus(gen: => TLInwardNode) {
to("sbus") { gen :=* TLBuffer(buffer) :=* outwardNode } to("sbus") { gen :=* TLBuffer(params.sbusBuffer) :=* outwardNode }
} }
} }

3
src/main/scala/subsystem/PeripheryBus.scala
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@ -12,6 +12,7 @@ case class PeripheryBusParams(
beatBytes: Int, beatBytes: Int,
blockBytes: Int, blockBytes: Int,
arithmeticAtomics: Boolean = true, arithmeticAtomics: Boolean = true,
bufferAtomics: BufferParams = BufferParams.default,
sbusCrossingType: SubsystemClockCrossing = SynchronousCrossing(), // relative to sbus sbusCrossingType: SubsystemClockCrossing = SynchronousCrossing(), // relative to sbus
frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
) extends HasTLBusParams ) extends HasTLBusParams
@ -92,7 +93,7 @@ class PeripheryBus(params: PeripheryBusParams)
def fromSystemBus(gen: => TLOutwardNode) { def fromSystemBus(gen: => TLOutwardNode) {
from("sbus") { from("sbus") {
(inwardNode (inwardNode
:*= TLBuffer(BufferParams.default) :*= TLBuffer(params.bufferAtomics)
:*= TLAtomicAutomata(arithmetic = params.arithmeticAtomics) :*= TLAtomicAutomata(arithmetic = params.arithmeticAtomics)
:*= gen) :*= gen)
} }

12
src/main/scala/subsystem/SystemBus.scala
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@ -8,7 +8,10 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
case class SystemBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusParams case class SystemBusParams(
beatBytes: Int,
blockBytes: Int,
pbusBuffer: BufferParams = BufferParams.none) extends HasTLBusParams
case object SystemBusKey extends Field[SystemBusParams] case object SystemBusKey extends Field[SystemBusParams]
@ -23,13 +26,12 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def busView = master_splitter.node.edges.in.head def busView = master_splitter.node.edges.in.head
def toPeripheryBus(buffer: BufferParams = BufferParams.none) def toPeripheryBus(gen: => TLNode): TLOutwardNode = {
(gen: => TLNode): TLOutwardNode = {
to("pbus") { to("pbus") {
(gen (gen
:= TLFIFOFixer(TLFIFOFixer.all) := TLFIFOFixer(TLFIFOFixer.all)
:= TLWidthWidget(params.beatBytes) := TLWidthWidget(params.beatBytes)
:= bufferTo(buffer)) := bufferTo(params.pbusBuffer))
} }
} }
@ -52,7 +54,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
} }
def toFixedWidthSlave[D,U,E,B <: Data] def toFixedWidthSlave[D,U,E,B <: Data]
(name: Option[String] = None, buffer: BufferParams = BufferParams.none) (name: Option[String] = None, buffer: BufferParams = BufferParams.default)
(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] = (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
to("slave" named name) { gen :*= fixedWidthTo(buffer) } to("slave" named name) { gen :*= fixedWidthTo(buffer) }