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subsystem: add some inter-wrapper buffer params

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This commit is contained in:
Henry Cook
2018-02-23 14:50:39 -08:00
parent ad823ef43c
commit 30c0635bb3
4 changed files with 20 additions and 12 deletions
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4
src/main/scala/subsystem/BaseSubsystem.scala
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@ -37,11 +37,11 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem {
val fbus = LazyModule(new FrontBus(p(FrontBusKey)))
// The sbus masters the pbus; here we convert TL-UH -> TL-UL
pbus.fromSystemBus() { sbus.toPeripheryBus() { pbus.crossTLIn } }
pbus.fromSystemBus { sbus.toPeripheryBus { pbus.crossTLIn } }
// The fbus masters the sbus; both are TL-UH or TL-C
FlipRendering { implicit p =>
fbus.toSystemBus() { sbus.fromFrontBus { fbus.crossTLOut } }
fbus.toSystemBus { sbus.fromFrontBus { fbus.crossTLOut } }
}
// The sbus masters the mbus; here we convert TL-C -> TL-UH