riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into hwacha-port

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This commit is contained in:
Yunsup Lee 2014-01-16 16:04:48 -08:00
commit 30b894c2c4
15 changed files with 966 additions and 1063 deletions
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4
rocket/src/main/scala/arbiter.scala
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@ -44,5 +44,9 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Modu
resp.bits.tag := io.mem.resp.bits.tag >> UInt(log2Up(n)) resp.bits.tag := io.mem.resp.bits.tag >> UInt(log2Up(n))
resp.bits.nack := io.mem.resp.bits.nack && tag_hit resp.bits.nack := io.mem.resp.bits.nack && tag_hit
resp.bits.replay := io.mem.resp.bits.replay && tag_hit resp.bits.replay := io.mem.resp.bits.replay && tag_hit
io.requestor(i).replay_next.valid := io.mem.replay_next.valid &&
io.mem.replay_next.bits(log2Up(n)-1,0) === UInt(log2Up(n))
io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> UInt(log2Up(n))
} }
} }

45
rocket/src/main/scala/consts.scala
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@ -21,32 +21,35 @@ trait ScalarOpConstants {
val PC_PCR = UInt(3, 2) val PC_PCR = UInt(3, 2)
val A1_X = Bits("b??", 2) val A1_X = Bits("b??", 2)
val A1_RS1 = UInt(0, 2) val A1_ZERO = UInt(0, 2)
val A1_ZERO = UInt(1, 2) val A1_RS1 = UInt(1, 2)
val A1_PC = UInt(2, 2) val A1_PCHI = UInt(2, 2)
val A1_PCHI = UInt(3, 2) val A1_PC = UInt(3, 2)
val IMM_X = Bits("b???", 3) val IMM_X = Bits("b???", 3)
val IMM_S = UInt(0, 3); val IMM_S = UInt(0, 3)
val IMM_SB = UInt(1, 3); val IMM_SB = UInt(1, 3)
val IMM_U = UInt(2, 3); val IMM_U = UInt(2, 3)
val IMM_UJ = UInt(3, 3); val IMM_UJ = UInt(3, 3)
val IMM_I = UInt(4, 3); val IMM_I = UInt(4, 3)
val IMM_Z = UInt(5, 3)
val A2_X = Bits("b??", 2) val A2_X = Bits("b??", 2)
val A2_RS2 = UInt(0, 2) val A2_ZERO = UInt(0, 2)
val A2_IMM = UInt(1, 2) val A2_FOUR = UInt(1, 2)
val A2_ZERO = UInt(2, 3) val A2_RS2 = UInt(2, 2)
val A2_FOUR = UInt(3, 3) val A2_IMM = UInt(3, 2)
val X = Bits("b?", 1) val X = Bool.DC
val N = Bits(0, 1) val N = Bool(false)
val Y = Bits(1, 1) val Y = Bool(true)
val WB_X = UInt("b??", 2) val NBYP = 4
val WB_ALU = UInt(0, 3); val SZ_BYP = log2Up(NBYP)
val WB_TSC = UInt(2, 3); val BYP_0 = 0
val WB_IRT = UInt(3, 3); val BYP_EX = 1
val BYP_MEM = 2
val BYP_DC = 3
val SZ_DW = 1 val SZ_DW = 1
val DW_X = X val DW_X = X
@ -54,7 +57,7 @@ trait ScalarOpConstants {
val DW_64 = Y val DW_64 = Y
val DW_XPR = Y val DW_XPR = Y
val RA = UInt(1, 5); val RA = UInt(1, 5)
} }
trait InterruptConstants { trait InterruptConstants {

700
rocket/src/main/scala/ctrl.scala
View File

@ -9,10 +9,9 @@ import Util._
class CtrlDpathIO extends Bundle() class CtrlDpathIO extends Bundle()
{ {
// outputs to datapath // outputs to datapath
val sel_pc = UInt(OUTPUT, 3); val sel_pc = UInt(OUTPUT, 3)
val killd = Bool(OUTPUT); val killd = Bool(OUTPUT)
val ren2 = Bool(OUTPUT); val ren = Vec.fill(2)(Bool(OUTPUT))
val ren1 = Bool(OUTPUT);
val sel_alu2 = UInt(OUTPUT, 3) val sel_alu2 = UInt(OUTPUT, 3)
val sel_alu1 = UInt(OUTPUT, 2) val sel_alu1 = UInt(OUTPUT, 2)
val sel_imm = UInt(OUTPUT, 3) val sel_imm = UInt(OUTPUT, 3)
@ -20,62 +19,62 @@ class CtrlDpathIO extends Bundle()
val fn_alu = UInt(OUTPUT, SZ_ALU_FN) val fn_alu = UInt(OUTPUT, SZ_ALU_FN)
val div_mul_val = Bool(OUTPUT) val div_mul_val = Bool(OUTPUT)
val div_mul_kill = Bool(OUTPUT) val div_mul_kill = Bool(OUTPUT)
val div_val = Bool(OUTPUT); val div_val = Bool(OUTPUT)
val div_kill = Bool(OUTPUT) val div_kill = Bool(OUTPUT)
val sel_wb = UInt(OUTPUT, 2) val csr = UInt(OUTPUT, 3)
val pcr = UInt(OUTPUT, 3) val sret = Bool(OUTPUT)
val eret = Bool(OUTPUT); val mem_load = Bool(OUTPUT)
val mem_load = Bool(OUTPUT);
val wb_load = Bool(OUTPUT) val wb_load = Bool(OUTPUT)
val ex_fp_val= Bool(OUTPUT); val ex_fp_val= Bool(OUTPUT)
val mem_fp_val= Bool(OUTPUT); val mem_fp_val= Bool(OUTPUT)
val ex_wen = Bool(OUTPUT); val ex_wen = Bool(OUTPUT)
val ex_jalr = Bool(OUTPUT) val ex_jalr = Bool(OUTPUT)
val ex_predicted_taken = Bool(OUTPUT) val ex_predicted_taken = Bool(OUTPUT)
val mem_wen = Bool(OUTPUT); val mem_wen = Bool(OUTPUT)
val wb_wen = Bool(OUTPUT); val wb_wen = Bool(OUTPUT)
val wb_valid = Bool(OUTPUT)
val ex_mem_type = Bits(OUTPUT, 3) val ex_mem_type = Bits(OUTPUT, 3)
val ex_rs2_val = Bool(OUTPUT) val ex_rs2_val = Bool(OUTPUT)
val ex_rocc_val = Bool(OUTPUT) val ex_rocc_val = Bool(OUTPUT)
val mem_rocc_val = Bool(OUTPUT) val mem_rocc_val = Bool(OUTPUT)
val mem_ll_bypass_rs1 = Bool(OUTPUT) val bypass = Vec.fill(2)(Bool(OUTPUT))
val mem_ll_bypass_rs2 = Bool(OUTPUT) val bypass_src = Vec.fill(2)(Bits(OUTPUT, SZ_BYP))
val ll_ready = Bool(OUTPUT)
// exception handling // exception handling
val exception = Bool(OUTPUT); val retire = Bool(OUTPUT)
val cause = UInt(OUTPUT, 6); val exception = Bool(OUTPUT)
val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault val cause = UInt(OUTPUT, 6)
val badvaddr_wen = Bool(OUTPUT) // high for a load/store access fault
// inputs from datapath // inputs from datapath
val inst = Bits(INPUT, 32); val inst = Bits(INPUT, 32)
val jalr_eq = Bool(INPUT) val jalr_eq = Bool(INPUT)
val ex_br_type = Bits(OUTPUT, SZ_BR) val ex_br_type = Bits(OUTPUT, SZ_BR)
val ex_br_taken = Bool(INPUT) val ex_br_taken = Bool(INPUT)
val div_mul_rdy = Bool(INPUT) val div_mul_rdy = Bool(INPUT)
val mem_ll_wb = Bool(INPUT) val ll_wen = Bool(INPUT)
val mem_ll_waddr = UInt(INPUT, 5) val ll_waddr = UInt(INPUT, 5)
val ex_waddr = UInt(INPUT, 5); // write addr from execute stage val ex_waddr = UInt(INPUT, 5)
val mem_waddr = UInt(INPUT, 5); // write addr from memory stage val mem_waddr = UInt(INPUT, 5)
val wb_waddr = UInt(INPUT, 5); // write addr from writeback stage val wb_waddr = UInt(INPUT, 5)
val status = new Status().asInput val status = new Status().asInput
val fp_sboard_clr = Bool(INPUT); val fp_sboard_clr = Bool(INPUT)
val fp_sboard_clra = UInt(INPUT, 5); val fp_sboard_clra = UInt(INPUT, 5)
val pcr_replay = Bool(INPUT) val csr_replay = Bool(INPUT)
} }
abstract trait DecodeConstants abstract trait DecodeConstants
{ {
val xpr64 = Y; val xpr64 = Y
val decode_default = val decode_default =
// fence.i // fence.i
// jalr mul_val | eret // jalr mul_val | sret
// fp_val | renx2 | div_val | | syscall // fp_val | renx2 | div_val | | syscall
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged // | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next // val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence // | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo // | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
List(N, X,X,BR_X, X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,WB_X, PCR.X,N,X,X,X,X,X,X) List(N, X,X,BR_X, X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,CSR.X,N,X,X,X,X,X)
val table: Array[(UInt, List[UInt])] val table: Array[(UInt, List[UInt])]
} }
@ -84,225 +83,222 @@ object XDecode extends DecodeConstants
{ {
val table = Array( val table = Array(
// fence.i // fence.i
// jalr mul_val | eret // jalr mul_val | sret
// fp_val | renx2 | div_val | | syscall // fp_val | renx2 | div_val | | syscall
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged // | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next // val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence // | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo // | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
JAL-> List(Y, N,N,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), JAL-> List(Y, N,N,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_PCHI,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_PCHI,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
LB-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LB-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,CSR.N,N,N,N,N,N,N),
LH-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LH-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,CSR.N,N,N,N,N,N,N),
LW-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LW-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,N),
LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,N),
LBU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LBU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,CSR.N,N,N,N,N,N,N),
LHU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LHU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,CSR.N,N,N,N,N,N,N),
LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,CSR.N,N,N,N,N,N,N),
SB-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), SB-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,CSR.N,N,N,N,N,N,N),
SH-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), SH-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,CSR.N,N,N,N,N,N,N),
SW-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), SW-> List(Y, N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N),
AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOXOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOXOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOXOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOXOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
LR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), LR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
LR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), LR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
SC_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), SC_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y),
SC_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,Y), SC_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y),
LUI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LUI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
XORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), XORI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
AND-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), AND-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
OR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), OR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
XOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), XOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N),
DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,WB_X, PCR.N,N,N,N,N,N,N,N), REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N),
SYSCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,Y,N,N,N,N), SCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,Y,N,N,N),
SETPCR-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.S,N,N,N,Y,N,N,N), SRET-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,Y,N,N,N,N),
CLEARPCR-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.C,N,N,N,Y,N,N,N), FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,Y,N),
ERET-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,Y,N,Y,N,N,N), FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,Y,N,N,Y,N,N),
FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,Y,N), CSRRW-> List(Y, N,N,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N),
FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,Y,N,N,N,Y,N,N), CSRRS-> List(Y, N,N,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N),
MFPCR-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.F,N,N,N,Y,N,N,N), CSRRC-> List(Y, N,N,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N),
MTPCR-> List(Y, N,N,BR_N, N,Y,N,A2_RS2, A1_ZERO,IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.T,N,N,N,Y,N,N,N), CSRRWI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N),
RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WB_TSC,PCR.N,N,N,N,N,N,N,N), CSRRSI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N),
RDCYCLE-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WB_TSC,PCR.N,N,N,N,N,N,N,N), CSRRCI-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N))
RDINSTRET-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WB_IRT,PCR.N,N,N,N,N,N,N,N))
} }
object FDecode extends DecodeConstants object FDecode extends DecodeConstants
{ {
val table = Array( val table = Array(
// fence.i // fence.i
// jalr mul_val | eret // jalr mul_val | sret
// fp_val | renx2 | div_val | | syscall // fp_val | renx2 | div_val | | syscall
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged // | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next // val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence // | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo // | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
FCVT_S_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSGNJN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSGNJN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMIN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMIN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMIN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMIN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMAX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMAX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMAX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMAX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMUL_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMUL_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMUL_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMUL_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FNMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMV_X_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FMV_X_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FMV_X_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FMV_X_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_W_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_W_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_WU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_WU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_WU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_WU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_L_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_L_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_L_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_L_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_LU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_LU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_LU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_LU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FEQ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FEQ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FEQ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FEQ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FLT_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLT_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FLT_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLT_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FLE_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLE_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FLE_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLE_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FMV_S_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMV_S_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FMV_D_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FMV_D_X-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_S_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_S_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_S_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_S_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_S_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCVT_D_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N), FCVT_D_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FRSR-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
FSSR-> List(Y, Y,N,BR_N, N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.N,N,N,N,N,N,N,N), FLD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,CSR.N,N,N,N,N,N,N),
FLW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), FSW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N),
FLD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), FSD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N))
FSW-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
FSD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N))
} }
object RoCCDecode extends DecodeConstants object RoCCDecode extends DecodeConstants
{ {
val table = Array( val table = Array(
// fence.i // fence.i
// jalr mul_val | eret // jalr mul_val | sret
// fp_val | renx2 | div_val | | syscall // fp_val | renx2 | div_val | | syscall
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged // | rocc_val | | renx1 s_alu1 mem_val | | wen | | |
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next // val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence // | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo // | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
CUSTOM0-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM0_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM0_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM0_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM0_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM0_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM0_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM1-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM1_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM1_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM1_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM1_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM1_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM1_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM2-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM2_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM2_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM2_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM2_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM2_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM2_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM3-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM3_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM3_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
CUSTOM3_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3_RD-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM3_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), CUSTOM3_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
CUSTOM3_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N)) CUSTOM3_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N))
} }
class Control(implicit conf: RocketConfiguration) extends Module class Control(implicit conf: RocketConfiguration) extends Module
@ -325,20 +321,16 @@ class Control(implicit conf: RocketConfiguration) extends Module
if (conf.fpu) decode_table ++= FDecode.table if (conf.fpu) decode_table ++= FDecode.table
if (!conf.rocc.isEmpty) decode_table ++= RoCCDecode.table if (!conf.rocc.isEmpty) decode_table ++= RoCCDecode.table
val logic = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table) val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table)
val cs = logic.map {
case b if b.inputs.head.getClass == classOf[Bool] => b.toBool
case u => u
}
val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs
val id_sel_alu2 :: id_sel_alu1 :: id_sel_imm :: (id_fn_dw: Bool) :: id_fn_alu :: cs1 = cs0 val id_sel_alu2 :: id_sel_alu1 :: id_sel_imm :: (id_fn_dw: Bool) :: id_fn_alu :: cs1 = cs0
val (id_mem_val: Bool) :: id_mem_cmd :: id_mem_type :: (id_mul_val: Bool) :: (id_div_val: Bool) :: (id_wen: Bool) :: id_sel_wb :: cs2 = cs1 val (id_mem_val: Bool) :: id_mem_cmd :: id_mem_type :: (id_mul_val: Bool) :: (id_div_val: Bool) :: (id_wen: Bool) :: cs2 = cs1
val id_pcr :: (id_fence_i: Bool) :: (id_eret: Bool) :: (id_syscall: Bool) :: (id_privileged: Bool) :: (id_replay_next: Bool) :: (id_fence: Bool) :: (id_amo: Bool) :: Nil = cs2 val id_csr :: (id_fence_i: Bool) :: (id_sret: Bool) :: (id_syscall: Bool) :: (id_replay_next: Bool) :: (id_fence: Bool) :: (id_amo: Bool) :: Nil = cs2
val ex_reg_xcpt_interrupt = Reg(init=Bool(false)) val ex_reg_xcpt_interrupt = Reg(init=Bool(false))
val ex_reg_valid = Reg(init=Bool(false)) val ex_reg_valid = Reg(init=Bool(false))
val ex_reg_eret = Reg(init=Bool(false)) val ex_reg_sret = Reg(init=Bool(false))
val ex_reg_wen = Reg(init=Bool(false)) val ex_reg_wen = Reg(init=Bool(false))
val ex_reg_fp_wen = Reg(init=Bool(false)) val ex_reg_fp_wen = Reg(init=Bool(false))
val ex_reg_flush_inst = Reg(init=Bool(false)) val ex_reg_flush_inst = Reg(init=Bool(false))
@ -351,7 +343,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val ex_reg_rocc_val = Reg(init=Bool(false)) val ex_reg_rocc_val = Reg(init=Bool(false))
val ex_reg_replay_next = Reg(init=Bool(false)) val ex_reg_replay_next = Reg(init=Bool(false))
val ex_reg_load_use = Reg(init=Bool(false)) val ex_reg_load_use = Reg(init=Bool(false))
val ex_reg_pcr = Reg(init=PCR.N) val ex_reg_csr = Reg(init=CSR.N)
val ex_reg_br_type = Reg(init=BR_N) val ex_reg_br_type = Reg(init=BR_N)
val ex_reg_mem_cmd = Reg(Bits()) val ex_reg_mem_cmd = Reg(Bits())
val ex_reg_mem_type = Reg(Bits()) val ex_reg_mem_type = Reg(Bits())
@ -359,7 +351,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val mem_reg_xcpt_interrupt = Reg(init=Bool(false)) val mem_reg_xcpt_interrupt = Reg(init=Bool(false))
val mem_reg_valid = Reg(init=Bool(false)) val mem_reg_valid = Reg(init=Bool(false))
val mem_reg_eret = Reg(init=Bool(false)) val mem_reg_sret = Reg(init=Bool(false))
val mem_reg_wen = Reg(init=Bool(false)) val mem_reg_wen = Reg(init=Bool(false))
val mem_reg_fp_wen = Reg(init=Bool(false)) val mem_reg_fp_wen = Reg(init=Bool(false))
val mem_reg_flush_inst = Reg(init=Bool(false)) val mem_reg_flush_inst = Reg(init=Bool(false))
@ -370,18 +362,18 @@ class Control(implicit conf: RocketConfiguration) extends Module
val mem_reg_rocc_val = Reg(init=Bool(false)) val mem_reg_rocc_val = Reg(init=Bool(false))
val mem_reg_replay = Reg(init=Bool(false)) val mem_reg_replay = Reg(init=Bool(false))
val mem_reg_replay_next = Reg(init=Bool(false)) val mem_reg_replay_next = Reg(init=Bool(false))
val mem_reg_pcr = Reg(init=PCR.N) val mem_reg_csr = Reg(init=CSR.N)
val mem_reg_cause = Reg(UInt()) val mem_reg_cause = Reg(UInt())
val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_slow_bypass = Reg(Bool())
val wb_reg_valid = Reg(init=Bool(false)) val wb_reg_valid = Reg(init=Bool(false))
val wb_reg_pcr = Reg(init=PCR.N) val wb_reg_csr = Reg(init=CSR.N)
val wb_reg_wen = Reg(init=Bool(false)) val wb_reg_wen = Reg(init=Bool(false))
val wb_reg_fp_wen = Reg(init=Bool(false)) val wb_reg_fp_wen = Reg(init=Bool(false))
val wb_reg_rocc_val = Reg(init=Bool(false)) val wb_reg_rocc_val = Reg(init=Bool(false))
val wb_reg_flush_inst = Reg(init=Bool(false)) val wb_reg_flush_inst = Reg(init=Bool(false))
val wb_reg_mem_val = Reg(init=Bool(false)) val wb_reg_mem_val = Reg(init=Bool(false))
val wb_reg_eret = Reg(init=Bool(false)) val wb_reg_sret = Reg(init=Bool(false))
val wb_reg_xcpt = Reg(init=Bool(false)) val wb_reg_xcpt = Reg(init=Bool(false))
val wb_reg_replay = Reg(init=Bool(false)) val wb_reg_replay = Reg(init=Bool(false))
val wb_reg_cause = Reg(UInt()) val wb_reg_cause = Reg(UInt())
@ -411,9 +403,23 @@ class Control(implicit conf: RocketConfiguration) extends Module
def checkExceptions(x: Seq[(Bool, UInt)]) = def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x)) (x.map(_._1).reduce(_||_), PriorityMux(x))
// flush pipeline on PCR writes that may have side effects val fp_csrs = CSRs.fcsr :: CSRs.frm :: CSRs.fflags :: Nil
val id_pcr_flush = id_pcr != PCR.N && id_pcr != PCR.F && val legal_csrs = if (conf.fpu) CSRs.all.toSet else CSRs.all.toSet -- fp_csrs
id_raddr1 != PCR.SUP0 && id_raddr1 != PCR.SUP1 && id_raddr1 != PCR.EPC
val id_csr_addr = io.dpath.inst(31,20)
val id_csr_en = id_csr != CSR.N
val id_csr_fp = Bool(conf.fpu) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
val id_csr_privileged = id_csr_en &&
(id_csr_addr(9,8) != UInt(0) ||
id_csr_addr(11,10) != UInt(0) && id_csr_wen)
val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr)
// flush pipeline on CSR writes that may have side effects
val id_csr_flush = {
val safe_csrs = CSRs.sup0 :: CSRs.sup1 :: CSRs.epc :: Nil
id_csr_en && id_csr_wen && DecodeLogic(id_csr_addr, legal_csrs -- safe_csrs, safe_csrs)
}
val id_privileged = id_sret || id_csr_privileged
// stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE) // stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
val id_amo_aq = io.dpath.inst(26) val id_amo_aq = io.dpath.inst(26)
@ -423,15 +429,15 @@ class Control(implicit conf: RocketConfiguration) extends Module
val id_fence_ok = io.dmem.ordered && !ex_reg_mem_val && val id_fence_ok = io.dmem.ordered && !ex_reg_mem_val &&
(Bool(conf.rocc.isEmpty) || !id_rocc_busy) (Bool(conf.rocc.isEmpty) || !id_rocc_busy)
id_reg_fence := id_fence_next || id_reg_fence && !id_fence_ok id_reg_fence := id_fence_next || id_reg_fence && !id_fence_ok
val id_do_fence = id_amo && id_amo_aq || id_fence_i || id_reg_fence && (id_mem_val || id_rocc_val) || id_pcr_flush val id_do_fence = id_amo && id_amo_aq || id_fence_i || id_reg_fence && (id_mem_val || id_rocc_val) || id_csr_flush
val (id_xcpt, id_cause) = checkExceptions(List( val (id_xcpt, id_cause) = checkExceptions(List(
(id_interrupt, id_interrupt_cause), (id_interrupt, id_interrupt_cause),
(io.imem.resp.bits.xcpt_ma, UInt(0)), (io.imem.resp.bits.xcpt_ma, UInt(0)),
(io.imem.resp.bits.xcpt_if, UInt(1)), (io.imem.resp.bits.xcpt_if, UInt(1)),
(!id_int_val.toBool, UInt(2)), (!id_int_val || id_csr_invalid, UInt(2)),
(id_privileged && !io.dpath.status.s, UInt(3)), (id_privileged && !io.dpath.status.s, UInt(3)),
(id_fp_val && !io.dpath.status.ef, UInt(4)), ((id_fp_val || id_csr_fp) && !io.dpath.status.ef, UInt(4)),
(id_syscall, UInt(6)), (id_syscall, UInt(6)),
(id_rocc_val && !io.dpath.status.er, UInt(12)))) (id_rocc_val && !io.dpath.status.er, UInt(12))))
@ -440,37 +446,37 @@ class Control(implicit conf: RocketConfiguration) extends Module
when (ctrl_killd) { when (ctrl_killd) {
ex_reg_jalr := Bool(false) ex_reg_jalr := Bool(false)
ex_reg_btb_hit := Bool(false); ex_reg_btb_hit := Bool(false)
ex_reg_div_mul_val := Bool(false) ex_reg_div_mul_val := Bool(false)
ex_reg_mem_val := Bool(false); ex_reg_mem_val := Bool(false)
ex_reg_valid := Bool(false); ex_reg_valid := Bool(false)
ex_reg_wen := Bool(false); ex_reg_wen := Bool(false)
ex_reg_fp_wen := Bool(false); ex_reg_fp_wen := Bool(false)
ex_reg_eret := Bool(false); ex_reg_sret := Bool(false)
ex_reg_flush_inst := Bool(false); ex_reg_flush_inst := Bool(false)
ex_reg_fp_val := Bool(false) ex_reg_fp_val := Bool(false)
ex_reg_rocc_val := Bool(false) ex_reg_rocc_val := Bool(false)
ex_reg_replay_next := Bool(false) ex_reg_replay_next := Bool(false)
ex_reg_load_use := Bool(false) ex_reg_load_use := Bool(false)
ex_reg_pcr := PCR.N ex_reg_csr := CSR.N
ex_reg_br_type := BR_N ex_reg_br_type := BR_N
ex_reg_xcpt := Bool(false) ex_reg_xcpt := Bool(false)
} }
.otherwise { .otherwise {
ex_reg_br_type := id_br_type; ex_reg_br_type := id_br_type
ex_reg_jalr := id_jalr ex_reg_jalr := id_jalr
ex_reg_btb_hit := io.imem.resp.bits.taken ex_reg_btb_hit := io.imem.resp.bits.taken && !id_jalr
ex_reg_div_mul_val := id_mul_val || id_div_val ex_reg_div_mul_val := id_mul_val || id_div_val
ex_reg_mem_val := id_mem_val.toBool; ex_reg_mem_val := id_mem_val.toBool
ex_reg_valid := Bool(true) ex_reg_valid := Bool(true)
ex_reg_pcr := id_pcr ex_reg_csr := id_csr
ex_reg_wen := id_wen && id_waddr != UInt(0) ex_reg_wen := id_wen
ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen
ex_reg_eret := id_eret.toBool; ex_reg_sret := id_sret
ex_reg_flush_inst := id_fence_i ex_reg_flush_inst := id_fence_i
ex_reg_fp_val := id_fp_val ex_reg_fp_val := id_fp_val
ex_reg_rocc_val := id_rocc_val.toBool ex_reg_rocc_val := id_rocc_val.toBool
ex_reg_replay_next := id_replay_next || id_pcr_flush ex_reg_replay_next := id_replay_next || id_csr_flush
ex_reg_load_use := id_load_use ex_reg_load_use := id_load_use
ex_reg_mem_cmd := id_mem_cmd ex_reg_mem_cmd := id_mem_cmd
ex_reg_mem_type := id_mem_type.toUInt ex_reg_mem_type := id_mem_type.toUInt
@ -484,9 +490,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val replay_ex_other = wb_dcache_miss && ex_reg_load_use || mem_reg_replay_next val replay_ex_other = wb_dcache_miss && ex_reg_load_use || mem_reg_replay_next
val replay_ex = replay_ex_structural || replay_ex_other val replay_ex = replay_ex_structural || replay_ex_other
ctrl_killx := take_pc_wb || replay_ex ctrl_killx := take_pc_wb || replay_ex
val take_pc_ex = Mux(ex_reg_jalr, val take_pc_ex = ex_reg_jalr && !io.dpath.jalr_eq || io.dpath.ex_br_taken
!(ex_reg_btb_hit && io.dpath.jalr_eq) && !replay_ex_other,
ex_reg_btb_hit != io.dpath.ex_br_taken)
// detect 2-cycle load-use delay for LB/LH/SC // detect 2-cycle load-use delay for LB/LH/SC
val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || AVec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type) val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || AVec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type)
@ -494,19 +498,19 @@ class Control(implicit conf: RocketConfiguration) extends Module
(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause), (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause),
(ex_reg_fp_val && io.fpu.illegal_rm, UInt(2)))) (ex_reg_fp_val && io.fpu.illegal_rm, UInt(2))))
mem_reg_replay := replay_ex && !take_pc_wb; mem_reg_replay := replay_ex && !take_pc_wb
mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb && !mem_reg_replay_next mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb && !mem_reg_replay_next
when (ex_xcpt) { mem_reg_cause := ex_cause } when (ex_xcpt) { mem_reg_cause := ex_cause }
mem_reg_div_mul_val := ex_reg_div_mul_val && io.dpath.div_mul_rdy mem_reg_div_mul_val := ex_reg_div_mul_val && io.dpath.div_mul_rdy
when (ctrl_killx) { when (ctrl_killx) {
mem_reg_valid := Bool(false); mem_reg_valid := Bool(false)
mem_reg_pcr := PCR.N mem_reg_csr := CSR.N
mem_reg_wen := Bool(false); mem_reg_wen := Bool(false)
mem_reg_fp_wen := Bool(false); mem_reg_fp_wen := Bool(false)
mem_reg_eret := Bool(false); mem_reg_sret := Bool(false)
mem_reg_mem_val := Bool(false); mem_reg_mem_val := Bool(false)
mem_reg_flush_inst := Bool(false); mem_reg_flush_inst := Bool(false)
mem_reg_fp_val := Bool(false) mem_reg_fp_val := Bool(false)
mem_reg_rocc_val := Bool(false) mem_reg_rocc_val := Bool(false)
mem_reg_replay_next := Bool(false) mem_reg_replay_next := Bool(false)
@ -514,12 +518,12 @@ class Control(implicit conf: RocketConfiguration) extends Module
} }
.otherwise { .otherwise {
mem_reg_valid := ex_reg_valid mem_reg_valid := ex_reg_valid
mem_reg_pcr := ex_reg_pcr mem_reg_csr := ex_reg_csr
mem_reg_wen := ex_reg_wen; mem_reg_wen := ex_reg_wen
mem_reg_fp_wen := ex_reg_fp_wen; mem_reg_fp_wen := ex_reg_fp_wen
mem_reg_eret := ex_reg_eret; mem_reg_sret := ex_reg_sret
mem_reg_mem_val := ex_reg_mem_val; mem_reg_mem_val := ex_reg_mem_val
mem_reg_flush_inst := ex_reg_flush_inst; mem_reg_flush_inst := ex_reg_flush_inst
mem_reg_fp_val := ex_reg_fp_val mem_reg_fp_val := ex_reg_fp_val
mem_reg_rocc_val := ex_reg_rocc_val mem_reg_rocc_val := ex_reg_rocc_val
mem_reg_replay_next := ex_reg_replay_next mem_reg_replay_next := ex_reg_replay_next
@ -534,10 +538,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
(mem_reg_mem_val && io.dmem.xcpt.pf.ld, UInt(10)), (mem_reg_mem_val && io.dmem.xcpt.pf.ld, UInt(10)),
(mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11)))) (mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11))))
val dcache_kill_mem = mem_reg_wen && io.dmem.replay_next.valid // structural hazard on writeback port
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen || mem_reg_rocc_val || mem_reg_pcr != PCR.N) val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem
val replay_mem = ll_wb_kill_mem || mem_reg_replay || fpu_kill_mem val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
val killm_common = ll_wb_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem
wb_reg_replay := replay_mem && !take_pc_wb wb_reg_replay := replay_mem && !take_pc_wb
@ -546,46 +550,44 @@ class Control(implicit conf: RocketConfiguration) extends Module
when (ctrl_killm) { when (ctrl_killm) {
wb_reg_valid := Bool(false) wb_reg_valid := Bool(false)
wb_reg_pcr := PCR.N wb_reg_csr := CSR.N
wb_reg_wen := Bool(false); wb_reg_wen := Bool(false)
wb_reg_fp_wen := Bool(false); wb_reg_fp_wen := Bool(false)
wb_reg_eret := Bool(false); wb_reg_sret := Bool(false)
wb_reg_flush_inst := Bool(false); wb_reg_flush_inst := Bool(false)
wb_reg_mem_val := Bool(false) wb_reg_mem_val := Bool(false)
wb_reg_div_mul_val := Bool(false); wb_reg_div_mul_val := Bool(false)
wb_reg_fp_val := Bool(false) wb_reg_fp_val := Bool(false)
wb_reg_rocc_val := Bool(false) wb_reg_rocc_val := Bool(false)
} }
.otherwise { .otherwise {
wb_reg_valid := mem_reg_valid wb_reg_valid := mem_reg_valid
wb_reg_pcr := mem_reg_pcr wb_reg_csr := mem_reg_csr
wb_reg_wen := mem_reg_wen; wb_reg_wen := mem_reg_wen
wb_reg_fp_wen := mem_reg_fp_wen; wb_reg_fp_wen := mem_reg_fp_wen
wb_reg_eret := mem_reg_eret && !mem_reg_replay wb_reg_sret := mem_reg_sret && !mem_reg_replay
wb_reg_flush_inst := mem_reg_flush_inst; wb_reg_flush_inst := mem_reg_flush_inst
wb_reg_mem_val := mem_reg_mem_val wb_reg_mem_val := mem_reg_mem_val
wb_reg_div_mul_val := mem_reg_div_mul_val wb_reg_div_mul_val := mem_reg_div_mul_val
wb_reg_fp_val := mem_reg_fp_val wb_reg_fp_val := mem_reg_fp_val
wb_reg_rocc_val := mem_reg_rocc_val wb_reg_rocc_val := mem_reg_rocc_val
} }
val replay_wb = io.dmem.resp.bits.nack || wb_reg_replay || val replay_wb_common =
io.dpath.pcr_replay || Bool(!conf.rocc.isEmpty) && wb_reg_rocc_val && !io.rocc.cmd.ready io.dmem.resp.bits.nack || wb_reg_replay || io.dpath.csr_replay
val wb_rocc_val = wb_reg_rocc_val && !replay_wb_common
val replay_wb = replay_wb_common || wb_reg_rocc_val && !io.rocc.cmd.ready
class Scoreboard(n: Int) class Scoreboard(n: Int)
{ {
val r = Reg(init=Bits(0, n))
private var _next = r
private var cur = r
var ens = Bool(false)
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr)) def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
def clear(en: Bool, addr: UInt): Unit = { def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
val m = ~mask(en, addr) def read(addr: UInt): Bool = r(addr)
update(en, _next & m) def readBypassed(addr: UInt): Bool = _next(addr)
//cur = cur & m
} private val r = Reg(init=Bits(0, n))
def read(addr: UInt) = r(addr) private var _next = r
def readBypassed(addr: UInt) = cur(addr) private var ens = Bool(false)
private def mask(en: Bool, addr: UInt) = Mux(en, UInt(1) << addr, UInt(0)) private def mask(en: Bool, addr: UInt) = Mux(en, UInt(1) << addr, UInt(0))
private def update(en: Bool, update: UInt) = { private def update(en: Bool, update: UInt) = {
_next = update _next = update
@ -596,7 +598,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val sboard = new Scoreboard(32) val sboard = new Scoreboard(32)
sboard.set((wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val) && io.dpath.wb_wen, io.dpath.wb_waddr) sboard.set((wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val) && io.dpath.wb_wen, io.dpath.wb_waddr)
sboard.clear(io.dpath.mem_ll_wb, io.dpath.mem_ll_waddr) sboard.clear(io.dpath.ll_wen, io.dpath.ll_waddr)
val id_stall_fpu = if (conf.fpu) { val id_stall_fpu = if (conf.fpu) {
val fp_sboard = new Scoreboard(32) val fp_sboard = new Scoreboard(32)
@ -604,24 +606,25 @@ class Control(implicit conf: RocketConfiguration) extends Module
fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra) fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra)
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
io.fpu.dec.ren1 && fp_sboard.readBypassed(id_raddr1) || id_csr_en && !io.fpu.fcsr_rdy ||
io.fpu.dec.ren2 && fp_sboard.readBypassed(id_raddr2) || io.fpu.dec.ren1 && fp_sboard.read(id_raddr1) ||
io.fpu.dec.ren3 && fp_sboard.readBypassed(id_raddr3) || io.fpu.dec.ren2 && fp_sboard.read(id_raddr2) ||
io.fpu.dec.wen && fp_sboard.readBypassed(id_waddr) io.fpu.dec.ren3 && fp_sboard.read(id_raddr3) ||
io.fpu.dec.wen && fp_sboard.read(id_waddr)
} else Bool(false) } else Bool(false)
// write cause to PCR on an exception // write CAUSE CSR on an exception
io.dpath.exception := wb_reg_xcpt io.dpath.exception := wb_reg_xcpt
io.dpath.cause := wb_reg_cause io.dpath.cause := wb_reg_cause
io.dpath.badvaddr_wen := wb_reg_xcpt && (wb_reg_cause === UInt(10) || wb_reg_cause === UInt(11)) io.dpath.badvaddr_wen := wb_reg_xcpt // don't care for non-memory exceptions
// control transfer from ex/wb // control transfer from ex/wb
take_pc_wb := replay_wb || wb_reg_xcpt || wb_reg_eret take_pc_wb := replay_wb || wb_reg_xcpt || wb_reg_sret
take_pc := take_pc_ex || take_pc_wb; take_pc := take_pc_ex || take_pc_wb
io.dpath.sel_pc := io.dpath.sel_pc :=
Mux(wb_reg_xcpt, PC_PCR, // exception Mux(wb_reg_xcpt, PC_PCR, // exception
Mux(wb_reg_eret, PC_PCR, // eret instruction Mux(wb_reg_sret, PC_PCR, // sret instruction
Mux(replay_wb, PC_WB, // replay Mux(replay_wb, PC_WB, // replay
PC_EX)))// branch/jal[r] PC_EX)))// branch/jal[r]
@ -629,6 +632,18 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.imem.req.bits.taken := !ex_reg_btb_hit || ex_reg_jalr io.imem.req.bits.taken := !ex_reg_btb_hit || ex_reg_jalr
io.imem.req.valid := take_pc io.imem.req.valid := take_pc
val bypassDst = Array(id_raddr1, id_raddr2)
val bypassSrc = Array.fill(NBYP)((Bool(true), UInt(0)))
bypassSrc(BYP_EX) = (ex_reg_wen, io.dpath.ex_waddr)
bypassSrc(BYP_MEM) = (mem_reg_wen && !mem_reg_mem_val, io.dpath.mem_waddr)
bypassSrc(BYP_DC) = (mem_reg_wen, io.dpath.mem_waddr)
val doBypass = bypassDst.map(d => bypassSrc.map(s => s._1 && s._2 === d))
for (i <- 0 until io.dpath.bypass.size) {
io.dpath.bypass(i) := doBypass(i).reduce(_||_)
io.dpath.bypass_src(i) := PriorityEncoder(doBypass(i))
}
// stall for RAW/WAW hazards on PCRs, loads, AMOs, and mul/div in execute stage. // stall for RAW/WAW hazards on PCRs, loads, AMOs, and mul/div in execute stage.
val data_hazard_ex = ex_reg_wen && val data_hazard_ex = ex_reg_wen &&
(id_renx1.toBool && id_raddr1 === io.dpath.ex_waddr || (id_renx1.toBool && id_raddr1 === io.dpath.ex_waddr ||
@ -639,7 +654,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr) io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr)
val id_ex_hazard = data_hazard_ex && (ex_reg_pcr != PCR.N || ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val || ex_reg_rocc_val) || val id_ex_hazard = data_hazard_ex && (ex_reg_csr != CSR.N || ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val || ex_reg_rocc_val) ||
fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val) fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val)
// stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage. // stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage.
@ -655,29 +670,22 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.mem_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.mem_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.mem_waddr) io.fpu.dec.wen && id_waddr === io.dpath.mem_waddr)
val id_mem_hazard = data_hazard_mem && (mem_reg_pcr != PCR.N || mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val || mem_reg_fp_val || mem_reg_rocc_val) || val id_mem_hazard = data_hazard_mem && (mem_reg_csr != CSR.N || mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val || mem_reg_fp_val || mem_reg_rocc_val) ||
fp_data_hazard_mem && mem_reg_fp_val fp_data_hazard_mem && mem_reg_fp_val
id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem) id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
val data_hazard_wb = wb_reg_wen &&
(id_raddr1 != UInt(0) && id_renx1 && (id_raddr1 === io.dpath.wb_waddr) ||
id_raddr2 != UInt(0) && id_renx2 && (id_raddr2 === io.dpath.wb_waddr) ||
id_waddr != UInt(0) && id_wen && (id_waddr === io.dpath.wb_waddr))
val fp_data_hazard_wb = wb_reg_fp_wen && val fp_data_hazard_wb = wb_reg_fp_wen &&
(io.fpu.dec.ren1 && id_raddr1 === io.dpath.wb_waddr || (io.fpu.dec.ren1 && id_raddr1 === io.dpath.wb_waddr ||
io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr) io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr)
val id_wb_hazard = data_hazard_wb && (wb_dcache_miss || wb_reg_div_mul_val || wb_reg_rocc_val) || val id_wb_hazard = fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val)
fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val)
io.dpath.mem_ll_bypass_rs1 := io.dpath.mem_ll_wb && io.dpath.mem_ll_waddr === id_raddr1
io.dpath.mem_ll_bypass_rs2 := io.dpath.mem_ll_wb && io.dpath.mem_ll_waddr === id_raddr2
val id_sboard_hazard = val id_sboard_hazard =
(id_raddr1 != UInt(0) && id_renx1 && sboard.read(id_raddr1) && !io.dpath.mem_ll_bypass_rs1 || (id_raddr1 != UInt(0) && id_renx1 && sboard.readBypassed(id_raddr1) ||
id_raddr2 != UInt(0) && id_renx2 && sboard.read(id_raddr2) && !io.dpath.mem_ll_bypass_rs2 || id_raddr2 != UInt(0) && id_renx2 && sboard.readBypassed(id_raddr2) ||
id_waddr != UInt(0) && id_wen && sboard.read(id_waddr)) id_waddr != UInt(0) && id_wen && sboard.readBypassed(id_waddr))
val ctrl_stalld = val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard || id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
@ -693,28 +701,28 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
io.dpath.wb_load := wb_reg_mem_val && wb_reg_wen io.dpath.wb_load := wb_reg_mem_val && wb_reg_wen
io.dpath.ren2 := id_renx2.toBool; io.dpath.ren(1) := id_renx2
io.dpath.ren1 := id_renx1.toBool; io.dpath.ren(0) := id_renx1
io.dpath.sel_alu2 := id_sel_alu2.toUInt io.dpath.sel_alu2 := id_sel_alu2.toUInt
io.dpath.sel_alu1 := id_sel_alu1.toUInt io.dpath.sel_alu1 := id_sel_alu1.toUInt
io.dpath.sel_imm := id_sel_imm.toUInt io.dpath.sel_imm := id_sel_imm.toUInt
io.dpath.fn_dw := id_fn_dw.toBool; io.dpath.fn_dw := id_fn_dw.toBool
io.dpath.fn_alu := id_fn_alu.toUInt io.dpath.fn_alu := id_fn_alu.toUInt
io.dpath.div_mul_val := ex_reg_div_mul_val io.dpath.div_mul_val := ex_reg_div_mul_val
io.dpath.div_mul_kill := mem_reg_div_mul_val && killm_common io.dpath.div_mul_kill := mem_reg_div_mul_val && killm_common
io.dpath.ex_fp_val:= ex_reg_fp_val; io.dpath.ex_fp_val:= ex_reg_fp_val
io.dpath.mem_fp_val:= mem_reg_fp_val; io.dpath.mem_fp_val:= mem_reg_fp_val
io.dpath.ex_jalr := ex_reg_jalr io.dpath.ex_jalr := ex_reg_jalr
io.dpath.ex_predicted_taken := ex_reg_btb_hit io.dpath.ex_predicted_taken := ex_reg_btb_hit
io.dpath.ex_wen := ex_reg_wen; io.dpath.ex_wen := ex_reg_wen
io.dpath.mem_wen := mem_reg_wen; io.dpath.mem_wen := mem_reg_wen
io.dpath.ll_ready := !wb_reg_wen
io.dpath.wb_wen := wb_reg_wen && !replay_wb io.dpath.wb_wen := wb_reg_wen && !replay_wb
io.dpath.wb_valid := wb_reg_valid && !replay_wb io.dpath.retire := wb_reg_valid && !replay_wb
io.dpath.sel_wb := id_sel_wb.toUInt io.dpath.csr := wb_reg_csr
io.dpath.pcr := wb_reg_pcr.toUInt io.dpath.sret := wb_reg_sret
io.dpath.eret := wb_reg_eret
io.dpath.ex_mem_type := ex_reg_mem_type io.dpath.ex_mem_type := ex_reg_mem_type
io.dpath.ex_br_type := ex_reg_br_type io.dpath.ex_br_type := ex_reg_br_type ^ ex_reg_btb_hit
io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_rocc_val io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_rocc_val
io.dpath.ex_rocc_val := ex_reg_rocc_val io.dpath.ex_rocc_val := ex_reg_rocc_val
io.dpath.mem_rocc_val := mem_reg_rocc_val io.dpath.mem_rocc_val := mem_reg_rocc_val
@ -729,5 +737,5 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dmem.req.bits.typ := ex_reg_mem_type io.dmem.req.bits.typ := ex_reg_mem_type
io.dmem.req.bits.phys := Bool(false) io.dmem.req.bits.phys := Bool(false)
io.rocc.cmd.valid := wb_reg_rocc_val io.rocc.cmd.valid := wb_rocc_val
} }

33
rocket/src/main/scala/decode.scala
View File

@ -14,28 +14,24 @@ object DecodeLogic
new Term(lit.value) new Term(lit.value)
} }
} }
def logic(addr: Bits, addrWidth: Int, cache: scala.collection.mutable.Map[Term,Bits], terms: Seq[Term]) = { def logic(addr: UInt, addrWidth: Int, cache: scala.collection.mutable.Map[Term,Bool], terms: Seq[Term]) = {
terms.map { t => terms.map { t =>
if (!cache.contains(t)) cache.getOrElseUpdate(t, (if (t.mask == 0) addr else addr & Bits(BigInt(2).pow(addrWidth)-(t.mask+1), addrWidth)) === Bits(t.value, addrWidth))
cache += t -> ((if (t.mask == 0) addr else addr & Lit(BigInt(2).pow(addrWidth)-(t.mask+1), addrWidth){Bits()}) === Lit(t.value, addrWidth){Bits()})
cache(t).toBool
}.foldLeft(Bool(false))(_||_) }.foldLeft(Bool(false))(_||_)
} }
def apply(addr: Bits, default: Iterable[Bits], mapping: Iterable[(Bits, Iterable[Bits])]) = { def apply[T <: Bits](addr: UInt, default: T, mapping: Iterable[(UInt, T)]): T = {
var map = mapping val cache = caches.getOrElseUpdate(Module.current, collection.mutable.Map[Term,Bool]())
var cache = scala.collection.mutable.Map[Term,Bits]() val dterm = term(default)
default map { d => val (keys, values) = mapping.unzip
val dterm = term(d)
val (keys, values) = map.unzip
val addrWidth = keys.map(_.getWidth).max val addrWidth = keys.map(_.getWidth).max
val terms = keys.toList.map(k => term(k)) val terms = keys.toList.map(k => term(k))
val termvalues = terms zip values.toList.map(v => term(v.head)) val termvalues = terms zip values.toList.map(term(_))
for (t <- keys.zip(terms).tails; if !t.isEmpty) for (t <- keys.zip(terms).tails; if !t.isEmpty)
for (u <- t.tail) for (u <- t.tail)
assert(!t.head._2.intersects(u._2), "DecodeLogic: keys " + t.head + " and " + u + " overlap") assert(!t.head._2.intersects(u._2), "DecodeLogic: keys " + t.head + " and " + u + " overlap")
val result = (0 until math.max(d.litOf.width, values.map(_.head.litOf.width).max)).map({ case (i: Int) => val result = (0 until default.litOf.width.max(values.map(_.litOf.width).max)).map({ case (i: Int) =>
val mint = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 1 }.map(_._1) val mint = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 1 }.map(_._1)
val maxt = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 0 }.map(_._1) val maxt = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 0 }.map(_._1)
val dc = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 1 }.map(_._1) val dc = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 1 }.map(_._1)
@ -49,10 +45,19 @@ object DecodeLogic
if (defbit == 0) bit else ~bit if (defbit == 0) bit else ~bit
} }
}).reverse.reduceRight(Cat(_,_)) }).reverse.reduceRight(Cat(_,_))
map = map map { case (x,y) => (x, y.tail) } default.fromBits(result)
result
} }
def apply[T <: Bits](addr: UInt, default: Iterable[T], mappingIn: Iterable[(UInt, Iterable[T])]): Iterable[T] = {
val mapping = collection.mutable.ArrayBuffer.fill(default.size)(collection.mutable.ArrayBuffer[(UInt, T)]())
for ((key, values) <- mappingIn)
for ((value, i) <- values zipWithIndex)
mapping(i) += key -> value
for ((thisDefault, thisMapping) <- default zip mapping)
yield apply(addr, thisDefault, thisMapping)
} }
def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool =
apply(addr, Bool.DC, trues.map(_ -> Bool(true)) ++ falses.map(_ -> Bool(false)))
private val caches = collection.mutable.Map[Module,collection.mutable.Map[Term,Bool]]()
} }
class Term(val value: BigInt, val mask: BigInt = 0) class Term(val value: BigInt, val mask: BigInt = 0)

199
rocket/src/main/scala/divider.scala
View File

@ -1,199 +0,0 @@
package rocket
import Chisel._
import ALU._
import Util._
class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Module {
val io = new MultiplierIO
val w = io.req.bits.in1.getWidth
val mulw = (w+mulUnroll-1)/mulUnroll*mulUnroll
val s_ready :: s_neg_inputs :: s_mul_busy :: s_div_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 7)
val state = Reg(init=s_ready)
val req = Reg(io.req.bits.clone)
val count = Reg(UInt(width = log2Up(w+1)))
val divby0 = Reg(Bool())
val neg_out = Reg(Bool())
val divisor = Reg(Bits(width = w+1)) // div only needs w bits
val remainder = Reg(Bits(width = 2*mulw+2)) // div only needs 2*w+1 bits
def sext(x: Bits, cmds: Vec[Bits]) = {
val sign = Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1)) && cmds.contains(io.req.bits.fn)
val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
(Cat(hi, x(w/2-1,0)), sign)
}
val (lhs_in, lhs_sign) = sext(io.req.bits.in1, AVec(FN_DIV, FN_REM, FN_MULH, FN_MULHSU))
val (rhs_in, rhs_sign) = sext(io.req.bits.in2, AVec(FN_DIV, FN_REM, FN_MULH))
val subtractor = remainder(2*w,w) - divisor(w,0)
val negated_remainder = -remainder(w-1,0)
when (state === s_neg_inputs) {
val isMul = AVec(FN_MUL, FN_MULH, FN_MULHU, FN_MULHSU).contains(req.fn)
state := Mux(isMul, s_mul_busy, s_div_busy)
when (remainder(w-1) || isMul) {
remainder := negated_remainder
}
when (divisor(w-1) || isMul) {
divisor := subtractor
}
}
when (state === s_neg_output) {
remainder := negated_remainder
state := s_done
}
when (state === s_move_rem) {
remainder := remainder(2*w, w+1)
state := Mux(neg_out, s_neg_output, s_done)
}
when (state === s_mul_busy) {
val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
val mplier = mulReg(mulw-1,0)
val accum = mulReg(2*mulw,mulw).toSInt
val mpcand = divisor.toSInt
val prod = mplier(mulUnroll-1,0) * mpcand + accum
val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt
remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt
count := count + 1
when (count === mulw/mulUnroll-1) {
state := s_done
when (AVec(FN_MULH, FN_MULHU, FN_MULHSU) contains req.fn) {
state := s_move_rem
}
}
}
when (state === s_div_busy) {
when (count === UInt(w)) {
state := Mux(neg_out && !divby0, s_neg_output, s_done)
when (AVec(FN_REM, FN_REMU) contains req.fn) {
state := s_move_rem
}
}
count := count + UInt(1)
val msb = subtractor(w)
divby0 := divby0 && !msb
remainder := Cat(Mux(msb, remainder(2*w-1,w), subtractor(w-1,0)), remainder(w-1,0), !msb)
val divisorMSB = Log2(divisor(w-1,0), w)
val dividendMSB = Log2(remainder(w-1,0), w)
val eOutPos = UInt(w-1) + divisorMSB - dividendMSB
val eOutZero = divisorMSB > dividendMSB
val eOut = count === UInt(0) && (eOutPos > 0 || eOutZero) && (divisorMSB != UInt(0) || divisor(0))
when (Bool(earlyOut) && eOut) {
val shift = Mux(eOutZero, UInt(w-1), eOutPos)
remainder := remainder(w-1,0) << shift
count := shift
}
}
when (io.resp.fire() || io.kill) {
state := s_ready
}
when (io.req.fire()) {
val isMul = AVec(FN_MUL, FN_MULH, FN_MULHU, FN_MULHSU).contains(io.req.bits.fn)
val isRem = AVec(FN_REM, FN_REMU).contains(io.req.bits.fn)
val mulState = Mux(lhs_sign, s_neg_inputs, s_mul_busy)
val divState = Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div_busy)
state := Mux(isMul, mulState, divState)
count := UInt(0)
neg_out := !isMul && Mux(isRem, lhs_sign, lhs_sign != rhs_sign)
divby0 := true
divisor := Cat(rhs_sign, rhs_in)
remainder := lhs_in
req := io.req.bits
}
io.resp.bits := req
io.resp.bits.data := Mux(req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
io.resp.valid := state === s_done
io.req.ready := state === s_ready
}
class Divider(earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Module {
val io = new MultiplierIO
val w = io.req.bits.in1.getWidth
val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 6)
val state = Reg(init=s_ready)
val count = Reg(UInt(width = log2Up(w+1)))
val divby0 = Reg(Bool())
val neg_out = Reg(Bool())
val r_req = Reg(io.req.bits)
val divisor = Reg(Bits())
val remainder = Reg(Bits(width = 2*w+1))
val subtractor = remainder(2*w,w) - divisor
def sext(x: Bits, cmds: Vec[Bits]) = {
val sign = Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1)) && cmds.contains(io.req.bits.fn)
val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
(Cat(hi, x(w/2-1,0)), sign)
}
val (lhs_in, lhs_sign) = sext(io.req.bits.in1, AVec(FN_DIV, FN_REM))
val (rhs_in, rhs_sign) = sext(io.req.bits.in2, AVec(FN_DIV, FN_REM))
val r_isRem = isMulFN(r_req.fn, FN_REM) || isMulFN(r_req.fn, FN_REMU)
when (state === s_neg_inputs) {
state := s_busy
when (remainder(w-1)) {
remainder := -remainder(w-1,0)
}
when (divisor(w-1)) {
divisor := subtractor(w-1,0)
}
}
when (state === s_neg_output) {
remainder := -remainder(w-1,0)
state := s_done
}
when (state === s_move_rem) {
remainder := remainder(2*w, w+1)
state := Mux(neg_out, s_neg_output, s_done)
}
when (state === s_busy) {
when (count === UInt(w)) {
state := Mux(r_isRem, s_move_rem, Mux(neg_out && !divby0, s_neg_output, s_done))
}
count := count + UInt(1)
val msb = subtractor(w)
divby0 := divby0 && !msb
remainder := Cat(Mux(msb, remainder(2*w-1,w), subtractor(w-1,0)), remainder(w-1,0), !msb)
val divisorMSB = Log2(divisor, w)
val dividendMSB = Log2(remainder(w-1,0), w)
val eOutPos = UInt(w-1, log2Up(2*w)) + divisorMSB - dividendMSB
val eOut = count === UInt(0) && eOutPos > 0 && (divisorMSB != UInt(0) || divisor(0))
when (Bool(earlyOut) && eOut) {
val shift = eOutPos(log2Up(w)-1,0)
remainder := remainder(w-1,0) << shift
count := shift
when (eOutPos(log2Up(w))) {
remainder := remainder(w-1,0) << w-1
count := w-1
}
}
}
when (io.resp.fire() || io.kill) {
state := s_ready
}
when (io.req.fire()) {
state := Mux(lhs_sign || rhs_sign, s_neg_inputs, s_busy)
count := UInt(0)
neg_out := Mux(AVec(FN_REM, FN_REMU).contains(io.req.bits.fn), lhs_sign, lhs_sign != rhs_sign)
divby0 := true
divisor := rhs_in
remainder := lhs_in
r_req := io.req.bits
}
io.resp.bits := r_req
io.resp.bits.data := Mux(r_req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
io.resp.valid := state === s_done
io.req.ready := state === s_ready
}

247
rocket/src/main/scala/dpath.scala
View File

@ -26,14 +26,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val ex_reg_sel_alu2 = Reg(UInt()) val ex_reg_sel_alu2 = Reg(UInt())
val ex_reg_sel_alu1 = Reg(UInt()) val ex_reg_sel_alu1 = Reg(UInt())
val ex_reg_sel_imm = Reg(UInt()) val ex_reg_sel_imm = Reg(UInt())
val ex_reg_ctrl_sel_wb = Reg(UInt())
val ex_reg_kill = Reg(Bool()) val ex_reg_kill = Reg(Bool())
val ex_reg_rs1_bypass = Reg(Bool()) val ex_reg_rs_bypass = Vec.fill(2)(Reg(Bool()))
val ex_reg_rs1_lsb = Reg(Bits()) val ex_reg_rs_lsb = Vec.fill(2)(Reg(Bits()))
val ex_reg_rs1_msb = Reg(Bits()) val ex_reg_rs_msb = Vec.fill(2)(Reg(Bits()))
val ex_reg_rs2_bypass = Reg(Bool())
val ex_reg_rs2_lsb = Reg(Bits())
val ex_reg_rs2_msb = Reg(Bits())
// memory definitions // memory definitions
val mem_reg_pc = Reg(UInt()) val mem_reg_pc = Reg(UInt())
@ -45,51 +41,54 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
// writeback definitions // writeback definitions
val wb_reg_pc = Reg(UInt()) val wb_reg_pc = Reg(UInt())
val wb_reg_inst = Reg(Bits()) val wb_reg_inst = Reg(Bits())
val wb_reg_waddr = Reg(UInt())
val wb_reg_wdata = Reg(Bits()) val wb_reg_wdata = Reg(Bits())
val wb_reg_ll_wb = Reg(init=Bool(false))
val wb_wdata = Bits() val wb_wdata = Bits()
val wb_reg_rs2 = Reg(Bits()) val wb_reg_rs2 = Reg(Bits())
val wb_wen = io.ctrl.wb_wen && io.ctrl.wb_valid || wb_reg_ll_wb
// instruction decode stage // instruction decode stage
val id_inst = io.imem.resp.bits.data val id_inst = io.imem.resp.bits.data
val id_pc = io.imem.resp.bits.pc val id_pc = io.imem.resp.bits.pc
val regfile_ = Mem(Bits(width = 64), 31) class RegFile {
def readRF(a: UInt) = regfile_(~a) private val rf = Mem(UInt(width = 64), 31)
def writeRF(a: UInt, d: Bits) = regfile_(~a) := d private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]()
private var canRead = true
def read(addr: UInt) = {
require(canRead)
reads += addr -> UInt()
reads.last._2 := rf(~addr)
reads.last._2
}
def write(addr: UInt, data: UInt) = {
canRead = false
when (addr != UInt(0)) {
rf(~addr) := data
for ((raddr, rdata) <- reads)
when (addr === raddr) { rdata := data }
}
}
}
val rf = new RegFile
val id_raddr1 = id_inst(19,15).toUInt; // RF read ports + bypass from WB stage
val id_raddr2 = id_inst(24,20).toUInt; val id_raddr = Vec(id_inst(19,15), id_inst(24,20))
val id_rs = id_raddr.map(rf.read _)
// bypass muxes
val id_rs1_zero = id_raddr1 === UInt(0)
val id_rs1_ex_bypass = io.ctrl.ex_wen && id_raddr1 === io.ctrl.ex_waddr
val id_rs1_mem_bypass = io.ctrl.mem_wen && id_raddr1 === io.ctrl.mem_waddr
val id_rs1_bypass = id_rs1_zero || id_rs1_ex_bypass || id_rs1_mem_bypass || io.ctrl.mem_ll_bypass_rs1
val id_rs1_bypass_src = Mux(id_rs1_zero, UInt(0), Mux(id_rs1_ex_bypass, UInt(1), Mux(io.ctrl.mem_load, UInt(3), UInt(2))))
val id_rs1 = Mux(wb_wen && id_raddr1 === wb_reg_waddr, wb_wdata, readRF(id_raddr1))
val id_rs2_zero = id_raddr2 === UInt(0)
val id_rs2_ex_bypass = io.ctrl.ex_wen && id_raddr2 === io.ctrl.ex_waddr
val id_rs2_mem_bypass = io.ctrl.mem_wen && id_raddr2 === io.ctrl.mem_waddr
val id_rs2_bypass = id_rs2_zero || id_rs2_ex_bypass || id_rs2_mem_bypass || io.ctrl.mem_ll_bypass_rs2
val id_rs2_bypass_src = Mux(id_rs2_zero, UInt(0), Mux(id_rs2_ex_bypass, UInt(1), Mux(io.ctrl.mem_load, UInt(3), UInt(2))))
val id_rs2 = Mux(wb_wen && id_raddr2 === wb_reg_waddr, wb_wdata, readRF(id_raddr2))
// immediate generation // immediate generation
def imm(sel: Bits, inst: Bits) = { def imm(sel: Bits, inst: Bits) = {
val sign = inst(31).toSInt val sign = inst(31).toSInt
val b30_20 = Mux(sel === IMM_U, inst(30,20).toSInt, sign) val b30_20 = Mux(sel === IMM_U, inst(30,20).toSInt, sign)
val b19_12 = Mux(sel != IMM_U && sel != IMM_UJ, sign, inst(19,12).toSInt) val b19_12 = Mux(sel != IMM_U && sel != IMM_UJ, sign, inst(19,12).toSInt)
val b11 = Mux(sel === IMM_U, SInt(0), val b11 = Mux(sel === IMM_U || sel === IMM_Z, SInt(0),
Mux(sel === IMM_UJ, inst(20).toSInt, Mux(sel === IMM_UJ, inst(20).toSInt,
Mux(sel === IMM_SB, inst(7).toSInt, sign))) Mux(sel === IMM_SB, inst(7).toSInt, sign)))
val b10_5 = Mux(sel === IMM_U, Bits(0), inst(30,25)) val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, Bits(0), inst(30,25))
val b4_1 = Mux(sel === IMM_U, Bits(0), val b4_1 = Mux(sel === IMM_U, Bits(0),
Mux(sel === IMM_S || sel === IMM_SB, inst(11,8), inst(24,21))) Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),
val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Bits(0))) Mux(sel === IMM_Z, inst(19,16), inst(24,21))))
val b0 = Mux(sel === IMM_S, inst(7),
Mux(sel === IMM_I, inst(20),
Mux(sel === IMM_Z, inst(15), Bits(0))))
Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).toSInt Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).toSInt
} }
@ -107,57 +106,49 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
ex_reg_sel_alu2 := io.ctrl.sel_alu2 ex_reg_sel_alu2 := io.ctrl.sel_alu2
ex_reg_sel_alu1 := io.ctrl.sel_alu1 ex_reg_sel_alu1 := io.ctrl.sel_alu1
ex_reg_sel_imm := io.ctrl.sel_imm ex_reg_sel_imm := io.ctrl.sel_imm
ex_reg_ctrl_sel_wb := io.ctrl.sel_wb ex_reg_rs_bypass := io.ctrl.bypass
ex_reg_rs1_bypass := id_rs1_bypass && io.ctrl.ren1 for (i <- 0 until id_rs.size) {
ex_reg_rs2_bypass := id_rs2_bypass && io.ctrl.ren2 when (io.ctrl.ren(i)) {
when (io.ctrl.ren1) { ex_reg_rs_lsb(i) := id_rs(i)(SZ_BYP-1,0)
ex_reg_rs1_lsb := id_rs1_bypass_src when (!io.ctrl.bypass(i)) {
when (!id_rs1_bypass) { ex_reg_rs_msb(i) := id_rs(i) >> SZ_BYP
ex_reg_rs1_lsb := id_rs1(id_rs1_bypass_src.getWidth-1,0)
ex_reg_rs1_msb := id_rs1(63,id_rs1_bypass_src.getWidth)
} }
} }
when (io.ctrl.ren2) { when (io.ctrl.bypass(i)) { ex_reg_rs_lsb(i) := io.ctrl.bypass_src(i) }
ex_reg_rs2_lsb := id_rs2_bypass_src
when (!id_rs2_bypass) {
ex_reg_rs2_lsb := id_rs2(id_rs2_bypass_src.getWidth-1,0)
ex_reg_rs2_msb := id_rs2(63,id_rs2_bypass_src.getWidth)
}
} }
} }
val ex_raddr1 = ex_reg_inst(19,15) val ex_raddr1 = ex_reg_inst(19,15)
val ex_raddr2 = ex_reg_inst(24,20) val ex_raddr2 = ex_reg_inst(24,20)
val dmem_resp_data = if (conf.fastLoadByte) io.dmem.resp.bits.data_subword else io.dmem.resp.bits.data val bypass = Vec.fill(NBYP)(Bits())
val ex_rs1 = bypass(BYP_0) := Bits(0)
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(3) && Bool(conf.fastLoadWord), dmem_resp_data, bypass(BYP_EX) := mem_reg_wdata
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(2), wb_reg_wdata, bypass(BYP_MEM) := wb_reg_wdata
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(1), mem_reg_wdata, bypass(BYP_DC) := (if (conf.fastLoadByte) io.dmem.resp.bits.data_subword
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(0), Bits(0), else if (conf.fastLoadWord) io.dmem.resp.bits.data
Mux(AVec(A1_ZERO, A1_PCHI) contains ex_reg_sel_alu1, Bits(0), else wb_reg_wdata)
Cat(ex_reg_rs1_msb, ex_reg_rs1_lsb))))))
val ex_rs2 =
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(3) && Bool(conf.fastLoadWord), dmem_resp_data,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(2), wb_reg_wdata,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(1), mem_reg_wdata,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(0), Bits(0),
Cat(ex_reg_rs2_msb, ex_reg_rs2_lsb)))))
val ex_rs = for (i <- 0 until id_rs.size)
yield Mux(ex_reg_rs_bypass(i), bypass(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
val ex_imm = imm(ex_reg_sel_imm, ex_reg_inst) val ex_imm = imm(ex_reg_sel_imm, ex_reg_inst)
val ex_op1_hi = Mux(AVec(A1_PC, A1_PCHI) contains ex_reg_sel_alu1, ex_reg_pc >> 12, ex_rs1 >> 12).toSInt val ex_op1_hi = MuxLookup(ex_reg_sel_alu1, ex_reg_pc.toSInt >> 12, Seq(
val ex_op1_lo = Mux(ex_reg_sel_alu1 === A1_PC, ex_reg_pc(11,0), ex_rs1(11,0)).toSInt A1_RS1 -> (ex_rs(0).toSInt >> 12),
A1_ZERO -> SInt(0)))
val ex_op1_lo = MuxLookup(ex_reg_sel_alu1, UInt(0), Seq(
A1_RS1 -> ex_rs(0)(11,0),
A1_PC -> ex_reg_pc(11,0)))
val ex_op1 = Cat(ex_op1_hi, ex_op1_lo) val ex_op1 = Cat(ex_op1_hi, ex_op1_lo)
val ex_op2 = Mux(ex_reg_sel_alu2 === A2_RS2, ex_rs2.toSInt, val ex_op2 = MuxLookup(ex_reg_sel_alu2, SInt(0), Seq(
Mux(ex_reg_sel_alu2 === A2_IMM, ex_imm, A2_RS2 -> ex_rs(1).toSInt,
Mux(ex_reg_sel_alu2 === A2_ZERO, SInt(0), A2_IMM -> ex_imm,
SInt(4)))) A2_FOUR -> SInt(4)))
val alu = Module(new ALU) val alu = Module(new ALU)
alu.io.dw := ex_reg_ctrl_fn_dw; alu.io.dw := ex_reg_ctrl_fn_dw
alu.io.fn := ex_reg_ctrl_fn_alu; alu.io.fn := ex_reg_ctrl_fn_alu
alu.io.in2 := ex_op2.toUInt alu.io.in2 := ex_op2.toUInt
alu.io.in1 := ex_op1.toUInt alu.io.in1 := ex_op1
// multiplier and divider // multiplier and divider
val div = Module(new MulDiv(mulUnroll = if (conf.fastMulDiv) 8 else 1, val div = Module(new MulDiv(mulUnroll = if (conf.fastMulDiv) 8 else 1,
@ -165,15 +156,13 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
div.io.req.valid := io.ctrl.div_mul_val div.io.req.valid := io.ctrl.div_mul_val
div.io.req.bits.dw := ex_reg_ctrl_fn_dw div.io.req.bits.dw := ex_reg_ctrl_fn_dw
div.io.req.bits.fn := ex_reg_ctrl_fn_alu div.io.req.bits.fn := ex_reg_ctrl_fn_alu
div.io.req.bits.in1 := ex_rs1 div.io.req.bits.in1 := ex_rs(0)
div.io.req.bits.in2 := ex_rs2 div.io.req.bits.in2 := ex_rs(1)
div.io.req.bits.tag := io.ctrl.ex_waddr div.io.req.bits.tag := io.ctrl.ex_waddr
div.io.kill := io.ctrl.div_mul_kill div.io.kill := io.ctrl.div_mul_kill
div.io.resp.ready := !io.ctrl.mem_wen
io.ctrl.div_mul_rdy := div.io.req.ready io.ctrl.div_mul_rdy := div.io.req.ready
io.fpu.fromint_data := ex_rs1 io.fpu.fromint_data := ex_rs(0)
io.ctrl.ex_waddr := ex_reg_inst(11,7)
def vaSign(a0: UInt, ea: Bits) = { def vaSign(a0: UInt, ea: Bits) = {
// efficient means to compress 64-bit VA into VADDR_BITS+1 bits // efficient means to compress 64-bit VA into VADDR_BITS+1 bits
@ -184,64 +173,54 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
Mux(a === SInt(-1) || a === SInt(-2), e === SInt(-1), Mux(a === SInt(-1) || a === SInt(-2), e === SInt(-1),
e(0))) e(0)))
} }
val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs1, ex_reg_pc) val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs(0), ex_reg_pc)
val ex_br_offset = Mux(io.ctrl.ex_predicted_taken && !io.ctrl.ex_jalr, SInt(4), ex_imm(19,0).toSInt) val ex_br_offset = Mux(io.ctrl.ex_predicted_taken, SInt(4), ex_imm(20,0).toSInt)
val ex_br64 = ex_br_base + ex_br_offset val ex_br64 = ex_br_base + ex_br_offset
val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs1, ex_br64), vaSign(ex_reg_pc, ex_br64)) val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs(0), ex_br64), vaSign(ex_reg_pc, ex_br64))
val ex_br_addr = Cat(ex_br_msb, ex_br64(VADDR_BITS-1,0)) val ex_br_addr = Cat(ex_br_msb, ex_br64(VADDR_BITS-1,0))
// D$ request interface (registered inside D$ module) // D$ request interface (registered inside D$ module)
// other signals (req_val, req_rdy) connect to control module // other signals (req_val, req_rdy) connect to control module
io.dmem.req.bits.addr := Cat(vaSign(ex_rs1, alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt
io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val) io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
require(io.dmem.req.bits.tag.getWidth >= 6) require(io.dmem.req.bits.tag.getWidth >= 6)
// processor control regfile read // processor control regfile read
val pcr = Module(new PCR) val pcr = Module(new CSRFile)
pcr.io.host <> io.host pcr.io.host <> io.host
pcr.io <> io.ctrl pcr.io <> io.ctrl
pcr.io <> io.fpu
pcr.io.pc := wb_reg_pc pcr.io.pc := wb_reg_pc
io.ctrl.pcr_replay := pcr.io.replay io.ctrl.csr_replay := pcr.io.replay
io.ptw.ptbr := pcr.io.ptbr io.ptw.ptbr := pcr.io.ptbr
io.ptw.invalidate := pcr.io.fatc io.ptw.invalidate := pcr.io.fatc
io.ptw.eret := io.ctrl.eret io.ptw.sret := io.ctrl.sret
io.ptw.status := pcr.io.status io.ptw.status := pcr.io.status
// branch resolution logic // branch resolution logic
io.ctrl.jalr_eq := ex_rs1 === id_pc.toSInt && ex_reg_inst(31,20) === UInt(0) io.ctrl.jalr_eq := ex_rs(0) === id_pc.toSInt && ex_reg_inst(31,20) === UInt(0)
io.ctrl.ex_br_taken := io.ctrl.ex_br_taken :=
Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs1 === ex_rs2, Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs(0) === ex_rs(1),
Mux(io.ctrl.ex_br_type === BR_NE, ex_rs1 != ex_rs2, Mux(io.ctrl.ex_br_type === BR_NE, ex_rs(0) != ex_rs(1),
Mux(io.ctrl.ex_br_type === BR_LT, ex_rs1.toSInt < ex_rs2.toSInt, Mux(io.ctrl.ex_br_type === BR_LT, ex_rs(0).toSInt < ex_rs(1).toSInt,
Mux(io.ctrl.ex_br_type === BR_GE, ex_rs1.toSInt >= ex_rs2.toSInt, Mux(io.ctrl.ex_br_type === BR_GE, ex_rs(0).toSInt >= ex_rs(1).toSInt,
Mux(io.ctrl.ex_br_type === BR_LTU, ex_rs1 < ex_rs2, Mux(io.ctrl.ex_br_type === BR_LTU, ex_rs(0) < ex_rs(1),
Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2, Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs(0) >= ex_rs(1),
io.ctrl.ex_br_type === BR_J)))))) io.ctrl.ex_br_type === BR_J))))))
val tsc_reg = WideCounter(64)
val irt_reg = WideCounter(64, io.ctrl.wb_valid)
// writeback select mux
val ex_wdata =
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg.value,
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg.value,
alu.io.out)).toBits // WB_ALU
// memory stage // memory stage
mem_reg_kill := ex_reg_kill mem_reg_kill := ex_reg_kill
when (!ex_reg_kill) { when (!ex_reg_kill) {
mem_reg_pc := ex_reg_pc mem_reg_pc := ex_reg_pc
mem_reg_inst := ex_reg_inst mem_reg_inst := ex_reg_inst
mem_reg_wdata := ex_wdata mem_reg_wdata := alu.io.out
when (io.ctrl.ex_rs2_val) {
mem_reg_rs2 := ex_rs2
} }
when (io.ctrl.ex_rs2_val) {
mem_reg_rs2 := ex_rs(1)
} }
// for load/use hazard detection (load byte/halfword) io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
io.ctrl.mem_waddr := mem_reg_inst(11,7)
// writeback arbitration // writeback arbitration
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
@ -250,28 +229,27 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
val dmem_resp_replay = io.dmem.resp.bits.replay && io.dmem.resp.bits.has_data val dmem_resp_replay = io.dmem.resp.bits.replay && io.dmem.resp.bits.has_data
val mem_ll_wdata = Bits() val ll_wdata = Bits()
mem_ll_wdata := div.io.resp.bits.data div.io.resp.ready := io.ctrl.ll_ready
io.ctrl.mem_ll_waddr := div.io.resp.bits.tag ll_wdata := div.io.resp.bits.data
io.ctrl.mem_ll_wb := div.io.resp.valid && !io.ctrl.mem_wen io.ctrl.ll_waddr := div.io.resp.bits.tag
io.ctrl.ll_wen := div.io.resp.fire()
if (!conf.rocc.isEmpty) { if (!conf.rocc.isEmpty) {
io.rocc.resp.ready := !io.ctrl.mem_wen && !io.ctrl.mem_rocc_val io.rocc.resp.ready := io.ctrl.ll_ready
when (io.rocc.resp.fire()) { when (io.rocc.resp.fire()) {
div.io.resp.ready := Bool(false) div.io.resp.ready := Bool(false)
mem_ll_wdata := io.rocc.resp.bits.data ll_wdata := io.rocc.resp.bits.data
io.ctrl.mem_ll_waddr := io.rocc.resp.bits.rd io.ctrl.ll_waddr := io.rocc.resp.bits.rd
io.ctrl.mem_ll_wb := Bool(true) io.ctrl.ll_wen := Bool(true)
} }
} }
when (dmem_resp_replay && dmem_resp_xpu) { when (dmem_resp_replay && dmem_resp_xpu) {
div.io.resp.ready := Bool(false) div.io.resp.ready := Bool(false)
if (!conf.rocc.isEmpty) if (!conf.rocc.isEmpty)
io.rocc.resp.ready := Bool(false) io.rocc.resp.ready := Bool(false)
mem_ll_wdata := io.dmem.resp.bits.data_subword io.ctrl.ll_waddr := dmem_resp_waddr
io.ctrl.mem_ll_waddr := dmem_resp_waddr io.ctrl.ll_wen := Bool(true)
io.ctrl.mem_ll_wb := Bool(true)
} }
when (io.ctrl.mem_ll_waddr === UInt(0)) { io.ctrl.mem_ll_wb := Bool(false) }
io.fpu.dmem_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.dmem_resp_val := dmem_resp_valid && dmem_resp_fpu
io.fpu.dmem_resp_data := io.dmem.resp.bits.data io.fpu.dmem_resp_data := io.dmem.resp.bits.data
@ -281,32 +259,28 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
// writeback stage // writeback stage
when (!mem_reg_kill) { when (!mem_reg_kill) {
wb_reg_pc := mem_reg_pc wb_reg_pc := mem_reg_pc
wb_reg_waddr := io.ctrl.mem_waddr
wb_reg_inst := mem_reg_inst wb_reg_inst := mem_reg_inst
wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata) wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata)
} }
when (io.ctrl.mem_rocc_val) { when (io.ctrl.mem_rocc_val) {
wb_reg_rs2 := mem_reg_rs2 wb_reg_rs2 := mem_reg_rs2
} }
wb_reg_ll_wb := io.ctrl.mem_ll_wb wb_wdata := Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data_subword,
when (io.ctrl.mem_ll_wb) { Mux(io.ctrl.ll_wen, ll_wdata,
wb_reg_waddr := io.ctrl.mem_ll_waddr Mux(io.ctrl.csr != CSR.N, pcr.io.rw.rdata,
wb_reg_wdata := mem_ll_wdata wb_reg_wdata)))
}
wb_wdata := Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword,
Mux(io.ctrl.pcr != PCR.N, pcr.io.rw.rdata,
wb_reg_wdata))
when (wb_wen) { writeRF(wb_reg_waddr, wb_wdata) } val wb_wen = io.ctrl.ll_wen || io.ctrl.wb_wen
io.ctrl.wb_waddr := wb_reg_waddr val wb_waddr = Mux(io.ctrl.ll_wen, io.ctrl.ll_waddr, io.ctrl.wb_waddr)
when (wb_wen) { rf.write(wb_waddr, wb_wdata) }
// scoreboard clear (for div/mul and D$ load miss writebacks) // scoreboard clear (for div/mul and D$ load miss writebacks)
io.ctrl.fp_sboard_clr := dmem_resp_replay && dmem_resp_fpu io.ctrl.fp_sboard_clr := dmem_resp_replay && dmem_resp_fpu
io.ctrl.fp_sboard_clra := dmem_resp_waddr io.ctrl.fp_sboard_clra := dmem_resp_waddr
// processor control regfile write // processor control regfile write
pcr.io.rw.addr := wb_reg_inst(19,15).toUInt pcr.io.rw.addr := wb_reg_inst(31,20)
pcr.io.rw.cmd := io.ctrl.pcr pcr.io.rw.cmd := io.ctrl.csr
pcr.io.rw.wdata := wb_reg_wdata pcr.io.rw.wdata := wb_reg_wdata
io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst) io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst)
@ -320,10 +294,15 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec, Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec,
wb_reg_pc)).toUInt // PC_WB wb_reg_pc)).toUInt // PC_WB
// for hazard/bypass opportunity detection
io.ctrl.ex_waddr := ex_reg_inst(11,7)
io.ctrl.mem_waddr := mem_reg_inst(11,7)
io.ctrl.wb_waddr := wb_reg_inst(11,7)
printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
tsc_reg(32,0), io.ctrl.wb_valid, wb_reg_pc, pcr.io.time(32,0), io.ctrl.retire, wb_reg_pc,
Mux(wb_wen, wb_reg_waddr, UInt(0)), wb_wdata, Mux(wb_wen, wb_waddr, UInt(0)), wb_wdata,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs1)), wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs2)), wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
wb_reg_inst, wb_reg_inst) wb_reg_inst, wb_reg_inst)
} }

192
rocket/src/main/scala/dpath_util.scala
View File

@ -9,14 +9,14 @@ import scala.math._
class DpathBTBIO extends Bundle class DpathBTBIO extends Bundle
{ {
val current_pc = UInt(INPUT, VADDR_BITS); val current_pc = UInt(INPUT, VADDR_BITS)
val hit = Bool(OUTPUT); val hit = Bool(OUTPUT)
val target = UInt(OUTPUT, VADDR_BITS); val target = UInt(OUTPUT, VADDR_BITS)
val wen = Bool(INPUT); val wen = Bool(INPUT)
val clr = Bool(INPUT); val clr = Bool(INPUT)
val invalidate = Bool(INPUT); val invalidate = Bool(INPUT)
val correct_pc = UInt(INPUT, VADDR_BITS); val correct_pc = UInt(INPUT, VADDR_BITS)
val correct_target = UInt(INPUT, VADDR_BITS); val correct_target = UInt(INPUT, VADDR_BITS)
} }
// fully-associative branch target buffer // fully-associative branch target buffer
@ -72,75 +72,47 @@ class Status extends Bundle {
val s = Bool() val s = Bool()
} }
object PCR object CSR
{ {
// commands // commands
val SZ = 3 val SZ = 2
val X = Bits("b???", 3) val X = Bits("b??", 2)
val N = Bits(0,3) val N = Bits(0,2)
val F = Bits(1,3) // mfpcr val W = Bits(1,2)
val T = Bits(4,3) // mtpcr val S = Bits(2,2)
val C = Bits(6,3) // clearpcr val C = Bits(3,2)
val S = Bits(7,3) // setpcr
// regs
val SUP0 = 0
val SUP1 = 1
val EPC = 2
val BADVADDR = 3
val PTBR = 4
val ASID = 5
val COUNT = 6
val COMPARE = 7
val EVEC = 8
val CAUSE = 9
val STATUS = 10
val HARTID = 11
val IMPL = 12
val FATC = 13
val SEND_IPI = 14
val CLR_IPI = 15
val STATS = 28
val RESET = 29
val TOHOST = 30
val FROMHOST = 31
} }
class PCR(implicit conf: RocketConfiguration) extends Module class CSRFile(implicit conf: RocketConfiguration) extends Module
{ {
val io = new Bundle { val io = new Bundle {
val host = new HTIFIO(conf.tl.ln.nClients) val host = new HTIFIO(conf.tl.ln.nClients)
val rw = new Bundle { val rw = new Bundle {
val addr = UInt(INPUT, log2Up(conf.nxpr)) val addr = UInt(INPUT, 12)
val cmd = Bits(INPUT, PCR.SZ) val cmd = Bits(INPUT, CSR.SZ)
val rdata = Bits(OUTPUT, conf.xprlen) val rdata = Bits(OUTPUT, conf.xprlen)
val wdata = Bits(INPUT, conf.xprlen) val wdata = Bits(INPUT, conf.xprlen)
} }
// there is a fixed constant related to this in PCRReq.addr
require(log2Up(conf.nxpr) == 5)
val status = new Status().asOutput val status = new Status().asOutput
val ptbr = UInt(OUTPUT, PADDR_BITS) val ptbr = UInt(OUTPUT, PADDR_BITS)
val evec = UInt(OUTPUT, VADDR_BITS+1) val evec = UInt(OUTPUT, VADDR_BITS+1)
val exception = Bool(INPUT) val exception = Bool(INPUT)
val retire = Bool(INPUT)
val cause = UInt(INPUT, 6) val cause = UInt(INPUT, 6)
val badvaddr_wen = Bool(INPUT) val badvaddr_wen = Bool(INPUT)
val pc = UInt(INPUT, VADDR_BITS+1) val pc = UInt(INPUT, VADDR_BITS+1)
val eret = Bool(INPUT) val sret = Bool(INPUT)
val ei = Bool(INPUT)
val di = Bool(INPUT)
val fatc = Bool(OUTPUT) val fatc = Bool(OUTPUT)
val irq_timer = Bool(OUTPUT)
val irq_ipi = Bool(OUTPUT)
val replay = Bool(OUTPUT) val replay = Bool(OUTPUT)
val time = UInt(OUTPUT, 64)
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
} }
import PCR._
val reg_epc = Reg(Bits(width = VADDR_BITS+1)) val reg_epc = Reg(Bits(width = VADDR_BITS+1))
val reg_badvaddr = Reg(Bits(width = VADDR_BITS)) val reg_badvaddr = Reg(Bits(width = VADDR_BITS))
val reg_evec = Reg(Bits(width = VADDR_BITS)) val reg_evec = Reg(Bits(width = VADDR_BITS))
val reg_count = WideCounter(32)
val reg_compare = Reg(Bits(width = 32)) val reg_compare = Reg(Bits(width = 32))
val reg_cause = Reg(Bits(width = io.cause.getWidth)) val reg_cause = Reg(Bits(width = io.cause.getWidth))
val reg_tohost = Reg(init=Bits(0, conf.xprlen)) val reg_tohost = Reg(init=Bits(0, conf.xprlen))
@ -150,12 +122,17 @@ class PCR(implicit conf: RocketConfiguration) extends Module
val reg_ptbr = Reg(UInt(width = PADDR_BITS)) val reg_ptbr = Reg(UInt(width = PADDR_BITS))
val reg_stats = Reg(init=Bool(false)) val reg_stats = Reg(init=Bool(false))
val reg_status = Reg(new Status) // reset down below val reg_status = Reg(new Status) // reset down below
val reg_time = WideCounter(64)
val reg_instret = WideCounter(64, io.retire)
val reg_fflags = Reg(UInt(width = 5))
val reg_frm = Reg(UInt(width = 3))
val r_irq_timer = Reg(init=Bool(false)) val r_irq_timer = Reg(init=Bool(false))
val r_irq_ipi = Reg(init=Bool(true)) val r_irq_ipi = Reg(init=Bool(true))
val cpu_req_valid = io.rw.cmd != CSR.N
val host_pcr_req_valid = Reg(Bool()) // don't reset val host_pcr_req_valid = Reg(Bool()) // don't reset
val host_pcr_req_fire = host_pcr_req_valid && io.rw.cmd === PCR.N val host_pcr_req_fire = host_pcr_req_valid && !cpu_req_valid
val host_pcr_rep_valid = Reg(Bool()) // don't reset val host_pcr_rep_valid = Reg(Bool()) // don't reset
val host_pcr_bits = Reg(io.host.pcr_req.bits) val host_pcr_bits = Reg(io.host.pcr_req.bits)
io.host.pcr_req.ready := !host_pcr_req_valid && !host_pcr_rep_valid io.host.pcr_req.ready := !host_pcr_req_valid && !host_pcr_rep_valid
@ -174,15 +151,26 @@ class PCR(implicit conf: RocketConfiguration) extends Module
io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
val addr = Mux(io.rw.cmd != PCR.N, io.rw.addr, host_pcr_bits.addr) val addr = Mux(cpu_req_valid, io.rw.addr, host_pcr_bits.addr | 0x500)
val wen = io.rw.cmd === PCR.T || io.rw.cmd === PCR.S || io.rw.cmd === PCR.C || val decoded_addr = {
host_pcr_req_fire && host_pcr_bits.rw val default = List(Bits("b" + ("?"*CSRs.all.size), CSRs.all.size))
val wdata = Mux(io.rw.cmd != PCR.N, io.rw.wdata, host_pcr_bits.data) val outs = for (i <- 0 until CSRs.all.size)
yield UInt(CSRs.all(i), addr.getWidth) -> List(UInt(BigInt(1) << i, CSRs.all.size))
val d = DecodeLogic(addr, default, outs).toArray
val a = Array.fill(CSRs.all.max+1)(null.asInstanceOf[Bool])
for (i <- 0 until CSRs.all.size)
a(CSRs.all(i)) = d(0)(i)
a
}
val wen = cpu_req_valid || host_pcr_req_fire && host_pcr_bits.rw
val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data)
io.status := reg_status io.status := reg_status
io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false), io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
Bool(false), Bool(false), Bool(false), Bool(false)) Bool(false), Bool(false), Bool(false), Bool(false))
io.fatc := wen && addr === FATC io.fatc := wen && decoded_addr(CSRs.fatc)
io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
io.ptbr := reg_ptbr io.ptbr := reg_ptbr
@ -202,41 +190,64 @@ class PCR(implicit conf: RocketConfiguration) extends Module
reg_cause := io.cause reg_cause := io.cause
} }
when (io.eret) { when (io.sret) {
reg_status.s := reg_status.ps reg_status.s := reg_status.ps
reg_status.ei := reg_status.pei reg_status.ei := reg_status.pei
} }
when (reg_count === reg_compare) { when (reg_time(reg_compare.getWidth-1,0) === reg_compare) {
r_irq_timer := Bool(true); r_irq_timer := true
} }
io.irq_timer := r_irq_timer; io.time := reg_time
io.irq_ipi := r_irq_ipi; io.host.ipi_req.valid := cpu_req_valid && decoded_addr(CSRs.send_ipi)
io.host.ipi_req.valid := io.rw.cmd === PCR.T && io.rw.addr === SEND_IPI
io.host.ipi_req.bits := io.rw.wdata io.host.ipi_req.bits := io.rw.wdata
io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
when (host_pcr_req_fire && !host_pcr_bits.rw && host_pcr_bits.addr === TOHOST) { reg_tohost := UInt(0) } when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.tohost)) { reg_tohost := UInt(0) }
val read_impl = Bits(2) val read_impl = Bits(2)
val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0) val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0)
io.rw.rdata := AVec[Bits](
reg_sup0, reg_sup1, reg_epc, reg_badvaddr, val read_mapping = Map[Int,Bits](
reg_ptbr, Bits(0)/*asid*/, reg_count, reg_compare, CSRs.fflags -> (if (conf.fpu) reg_fflags else UInt(0)),
reg_evec, reg_cause, io.status.toBits, io.host.id, CSRs.frm -> (if (conf.fpu) reg_frm else UInt(0)),
read_impl, read_impl/*x*/, read_impl/*x*/, read_impl/*x*/, CSRs.fcsr -> (if (conf.fpu) Cat(reg_frm, reg_fflags) else UInt(0)),
reg_stats/*x*/, reg_fromhost/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/, CSRs.cycle -> reg_time,
reg_stats/*x*/, reg_fromhost/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/, CSRs.time -> reg_time,
reg_stats/*x*/, reg_fromhost/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/, CSRs.instret -> reg_instret,
reg_stats, reg_fromhost/*x*/, reg_tohost, reg_fromhost CSRs.sup0 -> reg_sup0,
)(addr) CSRs.sup1 -> reg_sup1,
CSRs.epc -> reg_epc,
CSRs.badvaddr -> reg_badvaddr,
CSRs.ptbr -> read_ptbr,
CSRs.asid -> UInt(0),
CSRs.count -> reg_time,
CSRs.compare -> reg_compare,
CSRs.evec -> reg_evec,
CSRs.cause -> read_cause,
CSRs.status -> io.status.toBits,
CSRs.hartid -> io.host.id,
CSRs.impl -> read_impl,
CSRs.fatc -> read_impl, // don't care
CSRs.send_ipi -> read_impl, // don't care
CSRs.clear_ipi -> read_impl, // don't care
CSRs.stats -> reg_stats,
CSRs.tohost -> reg_tohost,
CSRs.fromhost -> reg_fromhost)
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
io.fcsr_rm := reg_frm
when (io.fcsr_flags.valid) {
reg_fflags := reg_fflags | io.fcsr_flags.bits
}
when (wen) { when (wen) {
when (addr === STATUS) { when (decoded_addr(CSRs.status)) {
val sr_wdata = Mux(io.rw.cmd === PCR.S, reg_status.toBits | wdata, val sr_wdata = Mux(io.rw.cmd === CSR.S, reg_status.toBits | wdata,
Mux(io.rw.cmd === PCR.C, reg_status.toBits & ~wdata, Mux(io.rw.cmd === CSR.C, reg_status.toBits & ~wdata,
wdata)) wdata))
reg_status := new Status().fromBits(sr_wdata) reg_status := new Status().fromBits(sr_wdata)
@ -247,17 +258,22 @@ class PCR(implicit conf: RocketConfiguration) extends Module
if (conf.rocc.isEmpty) reg_status.er := false if (conf.rocc.isEmpty) reg_status.er := false
if (!conf.fpu) reg_status.ef := false if (!conf.fpu) reg_status.ef := false
} }
when (addr === EPC) { reg_epc := wdata(VADDR_BITS,0).toSInt } when (io.rw.cmd != CSR.C && io.rw.cmd != CSR.S) {
when (addr === EVEC) { reg_evec := wdata(VADDR_BITS-1,0).toSInt } when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
when (addr === COUNT) { reg_count := wdata.toUInt } when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
when (addr === COMPARE) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false); } when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
when (addr === FROMHOST) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } } when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt }
when (addr === TOHOST) { when (reg_tohost === UInt(0)) { reg_tohost := wdata } } when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt }
when (addr === CLR_IPI) { r_irq_ipi := wdata(0) } when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
when (addr === SUP0) { reg_sup0 := wdata; } when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) }
when (addr === SUP1) { reg_sup1 := wdata; } when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
when (addr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt; } when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
when (addr === STATS) { reg_stats := wdata(0) } when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata }
when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata }
when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt }
when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
}
} }
io.host.ipi_rep.ready := Bool(true) io.host.ipi_rep.ready := Bool(true)

164
rocket/src/main/scala/fpu.scala
View File

@ -32,9 +32,7 @@ object FPConstants
val FCMD_MIN = Bits("b011000") val FCMD_MIN = Bits("b011000")
val FCMD_MAX = Bits("b011001") val FCMD_MAX = Bits("b011001")
val FCMD_MFTX = Bits("b011100") val FCMD_MFTX = Bits("b011100")
val FCMD_MFFSR = Bits("b011101")
val FCMD_MXTF = Bits("b011110") val FCMD_MXTF = Bits("b011110")
val FCMD_MTFSR = Bits("b011111")
val FCMD_MADD = Bits("b100100") val FCMD_MADD = Bits("b100100")
val FCMD_MSUB = Bits("b100101") val FCMD_MSUB = Bits("b100101")
val FCMD_NMSUB = Bits("b100110") val FCMD_NMSUB = Bits("b100110")
@ -43,7 +41,9 @@ object FPConstants
val FCMD_STORE = Bits("b111001") val FCMD_STORE = Bits("b111001")
val FCMD_X = Bits("b??????") val FCMD_X = Bits("b??????")
val FCMD_WIDTH = 6 val FCMD_WIDTH = 6
val FSR_WIDTH = 8
val RM_SZ = 3
val FLAGS_SZ = 5
} }
class FPUCtrlSigs extends Bundle class FPUCtrlSigs extends Bundle
@ -59,8 +59,6 @@ class FPUCtrlSigs extends Bundle
val fastpipe = Bool() val fastpipe = Bool()
val fma = Bool() val fma = Bool()
val round = Bool() val round = Bool()
val rdfsr = Bool()
val wrfsr = Bool()
} }
class FPUDecoder extends Module class FPUDecoder extends Module
@ -74,67 +72,65 @@ class FPUDecoder extends Module
val Y = Bool(true) val Y = Bool(true)
val X = Bool(false) val X = Bool(false)
val decoder = DecodeLogic(io.inst, val decoder = DecodeLogic(io.inst,
List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X), List (FCMD_X, X,X,X,X,X,X,X,X,X,X),
Array(FLW -> List(FCMD_LOAD, Y,N,N,N,Y,N,N,N,N,N,N,N), Array(FLW -> List(FCMD_LOAD, Y,N,N,N,Y,N,N,N,N,N),
FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N,N), FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N),
FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N,N,N), FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N),
FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N,N,N), FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N),
FMV_S_X -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,Y,N,N), FMV_S_X -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,Y),
FMV_D_X -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,Y,N,N), FMV_D_X -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,Y),
FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,Y),
FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,Y),
FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,Y),
FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N,Y,N,N), FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N,Y),
FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N,Y),
FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,Y),
FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,Y),
FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y,N,N), FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y),
FMV_X_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y,N,N), FMV_X_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y),
FMV_X_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y,N,N), FMV_X_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y),
FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N,Y,N,N), FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_W_D -> List(FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N,Y,N,N), FCVT_W_D -> List(FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N,Y),
FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N,Y,N,N), FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N,Y),
FCVT_L_D -> List(FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N,Y,N,N), FCVT_L_D -> List(FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N,Y),
FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N,Y,N,N), FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N,Y),
FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,Y,N,N,Y,N,N,Y,N,Y,N,N), FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,Y,N,N,Y,N,N,Y,N,Y),
FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,Y,N,N,N,N,N,Y,N,Y,N,N), FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,Y,N,N,N,N,N,Y,N,Y),
FEQ_S -> List(FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N,Y,N,N), FEQ_S -> List(FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N,Y),
FLT_S -> List(FCMD_LT, N,Y,Y,N,Y,N,Y,N,N,Y,N,N), FLT_S -> List(FCMD_LT, N,Y,Y,N,Y,N,Y,N,N,Y),
FLE_S -> List(FCMD_LE, N,Y,Y,N,Y,N,Y,N,N,Y,N,N), FLE_S -> List(FCMD_LE, N,Y,Y,N,Y,N,Y,N,N,Y),
FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,Y,N,N), FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,Y),
FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,Y,N,N), FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,Y),
FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,Y,N,N), FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,Y),
FSSR -> List(FCMD_MTFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,Y), FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,Y),
FRSR -> List(FCMD_MFFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,N), FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,Y),
FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,Y),
FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), FSGNJ_D -> List(FCMD_SGNJ, Y,Y,Y,N,N,N,N,Y,N,Y),
FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), FSGNJN_D -> List(FCMD_SGNJN, Y,Y,Y,N,N,N,N,Y,N,Y),
FSGNJ_D -> List(FCMD_SGNJ, Y,Y,Y,N,N,N,N,Y,N,Y,N,N), FSGNJX_D -> List(FCMD_SGNJX, Y,Y,Y,N,N,N,N,Y,N,Y),
FSGNJN_D -> List(FCMD_SGNJN, Y,Y,Y,N,N,N,N,Y,N,Y,N,N), FMIN_S -> List(FCMD_MIN, Y,Y,Y,N,Y,N,Y,Y,N,Y),
FSGNJX_D -> List(FCMD_SGNJX, Y,Y,Y,N,N,N,N,Y,N,Y,N,N), FMAX_S -> List(FCMD_MAX, Y,Y,Y,N,Y,N,Y,Y,N,Y),
FMIN_S -> List(FCMD_MIN, Y,Y,Y,N,Y,N,Y,Y,N,Y,N,N), FMIN_D -> List(FCMD_MIN, Y,Y,Y,N,N,N,Y,Y,N,Y),
FMAX_S -> List(FCMD_MAX, Y,Y,Y,N,Y,N,Y,Y,N,Y,N,N), FMAX_D -> List(FCMD_MAX, Y,Y,Y,N,N,N,Y,Y,N,Y),
FMIN_D -> List(FCMD_MIN, Y,Y,Y,N,N,N,Y,Y,N,Y,N,N), FADD_S -> List(FCMD_ADD, Y,Y,Y,N,Y,N,N,N,Y,Y),
FMAX_D -> List(FCMD_MAX, Y,Y,Y,N,N,N,Y,Y,N,Y,N,N), FSUB_S -> List(FCMD_SUB, Y,Y,Y,N,Y,N,N,N,Y,Y),
FADD_S -> List(FCMD_ADD, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N), FMUL_S -> List(FCMD_MUL, Y,Y,Y,N,Y,N,N,N,Y,Y),
FSUB_S -> List(FCMD_SUB, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N), FADD_D -> List(FCMD_ADD, Y,Y,Y,N,N,N,N,N,Y,Y),
FMUL_S -> List(FCMD_MUL, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N), FSUB_D -> List(FCMD_SUB, Y,Y,Y,N,N,N,N,N,Y,Y),
FADD_D -> List(FCMD_ADD, Y,Y,Y,N,N,N,N,N,Y,Y,N,N), FMUL_D -> List(FCMD_MUL, Y,Y,Y,N,N,N,N,N,Y,Y),
FSUB_D -> List(FCMD_SUB, Y,Y,Y,N,N,N,N,N,Y,Y,N,N), FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,Y,Y),
FMUL_D -> List(FCMD_MUL, Y,Y,Y,N,N,N,N,N,Y,Y,N,N), FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y),
FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,Y,Y),
FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y),
FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,N,N,N,N,Y,Y),
FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,N,N,N,N,Y,Y),
FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N), FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,N,N,N,N,Y,Y),
FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N), FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,N,N,N,N,Y,Y)
FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N),
FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N)
)) ))
val cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: round :: rdfsr :: wrfsr :: Nil = decoder val cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: round :: Nil = decoder
io.sigs.cmd := cmd io.sigs.cmd := cmd
io.sigs.wen := wen.toBool io.sigs.wen := wen.toBool
@ -147,14 +143,15 @@ class FPUDecoder extends Module
io.sigs.fastpipe := fastpipe.toBool io.sigs.fastpipe := fastpipe.toBool
io.sigs.fma := fma.toBool io.sigs.fma := fma.toBool
io.sigs.round := round.toBool io.sigs.round := round.toBool
io.sigs.rdfsr := rdfsr.toBool
io.sigs.wrfsr := wrfsr.toBool
} }
class DpathFPUIO extends Bundle { class DpathFPUIO extends Bundle {
val inst = Bits(OUTPUT, 32) val inst = Bits(OUTPUT, 32)
val fromint_data = Bits(OUTPUT, 64) val fromint_data = Bits(OUTPUT, 64)
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
val store_data = Bits(INPUT, 64) val store_data = Bits(INPUT, 64)
val toint_data = Bits(INPUT, 64) val toint_data = Bits(INPUT, 64)
@ -166,6 +163,7 @@ class DpathFPUIO extends Bundle {
class CtrlFPUIO extends Bundle { class CtrlFPUIO extends Bundle {
val valid = Bool(OUTPUT) val valid = Bool(OUTPUT)
val fcsr_rdy = Bool(INPUT)
val nack_mem = Bool(INPUT) val nack_mem = Bool(INPUT)
val illegal_rm = Bool(INPUT) val illegal_rm = Bool(INPUT)
val killx = Bool(OUTPUT) val killx = Bool(OUTPUT)
@ -182,7 +180,6 @@ class FPToInt extends Module
val single = Bool() val single = Bool()
val cmd = Bits(width = FCMD_WIDTH) val cmd = Bits(width = FCMD_WIDTH)
val rm = Bits(width = 3) val rm = Bits(width = 3)
val fsr = Bits(width = FSR_WIDTH)
val in1 = Bits(width = 65) val in1 = Bits(width = 65)
val in2 = Bits(width = 65) val in2 = Bits(width = 65)
override def clone = new Input().asInstanceOf[this.type] override def clone = new Input().asInstanceOf[this.type]
@ -211,7 +208,6 @@ class FPToInt extends Module
in.single := io.in.bits.single in.single := io.in.bits.single
in.cmd := io.in.bits.cmd in.cmd := io.in.bits.cmd
in.rm := io.in.bits.rm in.rm := io.in.bits.rm
in.fsr := io.in.bits.fsr
} }
val unrec_s = hardfloat.recodedFloatNToFloatN(in.in1, 23, 9) val unrec_s = hardfloat.recodedFloatNToFloatN(in.in1, 23, 9)
@ -228,9 +224,6 @@ class FPToInt extends Module
io.out.bits.toint := Mux(in.single, Cat(Fill(32, unrec_s(31)), unrec_s), unrec_d) io.out.bits.toint := Mux(in.single, Cat(Fill(32, unrec_s(31)), unrec_s), unrec_d)
io.out.bits.exc := Bits(0) io.out.bits.exc := Bits(0)
when (in.cmd === FCMD_MTFSR || in.cmd === FCMD_MFFSR) {
io.out.bits.toint := io.in.bits.fsr
}
when (in.cmd === FCMD_CVT_W_FMT || in.cmd === FCMD_CVT_WU_FMT) { when (in.cmd === FCMD_CVT_W_FMT || in.cmd === FCMD_CVT_WU_FMT) {
io.out.bits.toint := Cat(Fill(32, d2i._1(31)), d2i._1(31,0)) io.out.bits.toint := Cat(Fill(32, d2i._1(31)), d2i._1(31,0))
io.out.bits.exc := d2i._2 io.out.bits.exc := d2i._2
@ -472,9 +465,6 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module
val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12) val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12)
val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1), rec_s), rec_d) val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1), rec_s), rec_d)
val fsr_rm = Reg(Bits(width = 3))
val fsr_exc = Reg(Bits(width = 5))
// regfile // regfile
val regfile = Mem(Bits(width = 65), 32) val regfile = Mem(Bits(width = 65), 32)
when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded } when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded }
@ -482,13 +472,12 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module
val ex_rs1 = regfile(ex_reg_inst(19,15)) val ex_rs1 = regfile(ex_reg_inst(19,15))
val ex_rs2 = regfile(ex_reg_inst(24,20)) val ex_rs2 = regfile(ex_reg_inst(24,20))
val ex_rs3 = regfile(ex_reg_inst(31,27)) val ex_rs3 = regfile(ex_reg_inst(31,27))
val ex_rm = Mux(ex_reg_inst(14,12) === Bits(7), fsr_rm, ex_reg_inst(14,12)) val ex_rm = Mux(ex_reg_inst(14,12) === Bits(7), io.dpath.fcsr_rm, ex_reg_inst(14,12))
val fpiu = Module(new FPToInt) val fpiu = Module(new FPToInt)
fpiu.io.in.valid := ex_reg_valid && ctrl.toint fpiu.io.in.valid := ex_reg_valid && ctrl.toint
fpiu.io.in.bits := ctrl fpiu.io.in.bits := ctrl
fpiu.io.in.bits.rm := ex_rm fpiu.io.in.bits.rm := ex_rm
fpiu.io.in.bits.fsr := Cat(fsr_rm, fsr_exc)
fpiu.io.in.bits.in1 := ex_rs1 fpiu.io.in.bits.in1 := ex_rs1
fpiu.io.in.bits.in2 := ex_rs2 fpiu.io.in.bits.in2 := ex_rs2
@ -576,24 +565,17 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module
val wexc = Vec(pipes.map(_.wexc))(wsrc) val wexc = Vec(pipes.map(_.wexc))(wsrc)
when (wen(0)) { regfile(waddr(4,0)) := wdata } when (wen(0)) { regfile(waddr(4,0)) := wdata }
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
when (wb_reg_valid && wb_ctrl.toint || wen(0)) { io.dpath.fcsr_flags.valid := wb_toint_valid || wen(0)
fsr_exc := fsr_exc | io.dpath.fcsr_flags.bits :=
Fill(fsr_exc.getWidth, wb_reg_valid && wb_ctrl.toint) & wb_toint_exc | Mux(wb_toint_valid, wb_toint_exc, UInt(0)) |
Fill(fsr_exc.getWidth, wen(0)) & wexc Mux(wen(0), wexc, UInt(0))
}
val mem_fsr_wdata = RegEnable(io.dpath.fromint_data(FSR_WIDTH-1,0), ex_reg_valid && ctrl.wrfsr)
val wb_fsr_wdata = RegEnable(mem_fsr_wdata, mem_reg_valid && mem_ctrl.wrfsr)
when (wb_reg_valid && wb_ctrl.wrfsr) {
fsr_exc := wb_fsr_wdata
fsr_rm := wb_fsr_wdata >> fsr_exc.getWidth
}
val fp_inflight = wb_reg_valid && wb_ctrl.toint || wen.orR val fp_inflight = wb_reg_valid && wb_ctrl.toint || wen.orR
val fsr_busy = mem_ctrl.rdfsr && fp_inflight || wb_reg_valid && wb_ctrl.wrfsr
val units_busy = mem_reg_valid && mem_ctrl.fma && Reg(next=Mux(ctrl.single, io.sfma.valid, io.dfma.valid)) val units_busy = mem_reg_valid && mem_ctrl.fma && Reg(next=Mux(ctrl.single, io.sfma.valid, io.dfma.valid))
io.ctrl.nack_mem := fsr_busy || units_busy || write_port_busy io.ctrl.fcsr_rdy := !fp_inflight
io.ctrl.nack_mem := units_busy || write_port_busy
io.ctrl.dec <> fp_decoder.io.sigs io.ctrl.dec <> fp_decoder.io.sigs
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(Bool(false))(_||_) def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(Bool(false))(_||_)
io.ctrl.sboard_set := wb_reg_valid && Reg(next=useScoreboard(_._1.cond(mem_ctrl))) io.ctrl.sboard_set := wb_reg_valid && Reg(next=useScoreboard(_._1.cond(mem_ctrl)))

4
rocket/src/main/scala/icache.scala
View File

@ -160,11 +160,11 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module
val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits) val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits)
val s0_valid = io.req.valid || s1_valid && stall val s0_valid = io.req.valid || s1_valid && stall
val s0_pgoff = Mux(io.req.valid, io.req.bits.idx, s1_pgoff) val s0_pgoff = Mux(s1_valid && stall, s1_pgoff, io.req.bits.idx)
s1_valid := io.req.valid && rdy || s1_valid && stall && !io.req.bits.kill s1_valid := io.req.valid && rdy || s1_valid && stall && !io.req.bits.kill
when (io.req.valid && rdy) { when (io.req.valid && rdy) {
s1_pgoff := s0_pgoff s1_pgoff := io.req.bits.idx
} }
s2_valid := s1_valid && rdy && !io.req.bits.kill || io.resp.valid && stall s2_valid := s1_valid && rdy && !io.req.bits.kill || io.resp.valid && stall

117
rocket/src/main/scala/instructions.scala
View File

@ -3,11 +3,10 @@ package rocket
import Chisel._ import Chisel._
import Node._ import Node._
object Instructions
{
/* Automatically generated by parse-opcodes */ /* Automatically generated by parse-opcodes */
def JAL = Bits("b?????????????????????????1100111") object Instructions {
def JALR = Bits("b?????????????????000?????1101111") def JAL = Bits("b?????????????????????????1101111")
def JALR = Bits("b?????????????????000?????1100111")
def BEQ = Bits("b?????????????????000?????1100011") def BEQ = Bits("b?????????????????000?????1100011")
def BNE = Bits("b?????????????????001?????1100011") def BNE = Bits("b?????????????????001?????1100011")
def BLT = Bits("b?????????????????100?????1100011") def BLT = Bits("b?????????????????100?????1100011")
@ -35,14 +34,6 @@ object Instructions
def SRA = Bits("b0100000??????????101?????0110011") def SRA = Bits("b0100000??????????101?????0110011")
def OR = Bits("b0000000??????????110?????0110011") def OR = Bits("b0000000??????????110?????0110011")
def AND = Bits("b0000000??????????111?????0110011") def AND = Bits("b0000000??????????111?????0110011")
def MUL = Bits("b0000001??????????000?????0110011")
def MULH = Bits("b0000001??????????001?????0110011")
def MULHSU = Bits("b0000001??????????010?????0110011")
def MULHU = Bits("b0000001??????????011?????0110011")
def DIV = Bits("b0000001??????????100?????0110011")
def DIVU = Bits("b0000001??????????101?????0110011")
def REM = Bits("b0000001??????????110?????0110011")
def REMU = Bits("b0000001??????????111?????0110011")
def ADDIW = Bits("b?????????????????000?????0011011") def ADDIW = Bits("b?????????????????000?????0011011")
def SLLIW = Bits("b0000000??????????001?????0011011") def SLLIW = Bits("b0000000??????????001?????0011011")
def SRLIW = Bits("b0000000??????????101?????0011011") def SRLIW = Bits("b0000000??????????101?????0011011")
@ -52,11 +43,6 @@ object Instructions
def SLLW = Bits("b0000000??????????001?????0111011") def SLLW = Bits("b0000000??????????001?????0111011")
def SRLW = Bits("b0000000??????????101?????0111011") def SRLW = Bits("b0000000??????????101?????0111011")
def SRAW = Bits("b0100000??????????101?????0111011") def SRAW = Bits("b0100000??????????101?????0111011")
def MULW = Bits("b0000001??????????000?????0111011")
def DIVW = Bits("b0000001??????????100?????0111011")
def DIVUW = Bits("b0000001??????????101?????0111011")
def REMW = Bits("b0000001??????????110?????0111011")
def REMUW = Bits("b0000001??????????111?????0111011")
def LB = Bits("b?????????????????000?????0000011") def LB = Bits("b?????????????????000?????0000011")
def LH = Bits("b?????????????????001?????0000011") def LH = Bits("b?????????????????001?????0000011")
def LW = Bits("b?????????????????010?????0000011") def LW = Bits("b?????????????????010?????0000011")
@ -68,6 +54,21 @@ object Instructions
def SH = Bits("b?????????????????001?????0100011") def SH = Bits("b?????????????????001?????0100011")
def SW = Bits("b?????????????????010?????0100011") def SW = Bits("b?????????????????010?????0100011")
def SD = Bits("b?????????????????011?????0100011") def SD = Bits("b?????????????????011?????0100011")
def FENCE = Bits("b?????????????????000?????0001111")
def FENCE_I = Bits("b?????????????????001?????0001111")
def MUL = Bits("b0000001??????????000?????0110011")
def MULH = Bits("b0000001??????????001?????0110011")
def MULHSU = Bits("b0000001??????????010?????0110011")
def MULHU = Bits("b0000001??????????011?????0110011")
def DIV = Bits("b0000001??????????100?????0110011")
def DIVU = Bits("b0000001??????????101?????0110011")
def REM = Bits("b0000001??????????110?????0110011")
def REMU = Bits("b0000001??????????111?????0110011")
def MULW = Bits("b0000001??????????000?????0111011")
def DIVW = Bits("b0000001??????????100?????0111011")
def DIVUW = Bits("b0000001??????????101?????0111011")
def REMW = Bits("b0000001??????????110?????0111011")
def REMUW = Bits("b0000001??????????111?????0111011")
def AMOADD_W = Bits("b00000????????????010?????0101111") def AMOADD_W = Bits("b00000????????????010?????0101111")
def AMOXOR_W = Bits("b00100????????????010?????0101111") def AMOXOR_W = Bits("b00100????????????010?????0101111")
def AMOOR_W = Bits("b01000????????????010?????0101111") def AMOOR_W = Bits("b01000????????????010?????0101111")
@ -90,18 +91,15 @@ object Instructions
def AMOSWAP_D = Bits("b00001????????????011?????0101111") def AMOSWAP_D = Bits("b00001????????????011?????0101111")
def LR_D = Bits("b00010??00000?????011?????0101111") def LR_D = Bits("b00010??00000?????011?????0101111")
def SC_D = Bits("b00011????????????011?????0101111") def SC_D = Bits("b00011????????????011?????0101111")
def FENCE = Bits("b?????????????????000?????0001111") def SCALL = Bits("b00000000000000000000000001110011")
def FENCE_I = Bits("b?????????????????001?????0001111") def SBREAK = Bits("b00000000000100000000000001110011")
def SYSCALL = Bits("b00000000000000000000000001110111") def SRET = Bits("b10000000000000000000000001110011")
def BREAK = Bits("b00000000000000000001000001110111") def CSRRW = Bits("b?????????????????001?????1110011")
def RDCYCLE = Bits("b00000000000000000100?????1110111") def CSRRS = Bits("b?????????????????010?????1110011")
def RDTIME = Bits("b00000010000000000100?????1110111") def CSRRC = Bits("b?????????????????011?????1110011")
def RDINSTRET = Bits("b00000100000000000100?????1110111") def CSRRWI = Bits("b?????????????????101?????1110011")
def MTPCR = Bits("b0000000??????????000?????1110011") def CSRRSI = Bits("b?????????????????110?????1110011")
def MFPCR = Bits("b000000000000?????001?????1110011") def CSRRCI = Bits("b?????????????????111?????1110011")
def SETPCR = Bits("b?????????????????010?????1110011")
def CLEARPCR = Bits("b?????????????????011?????1110011")
def ERET = Bits("b00000000000000000100000001110011")
def FADD_S = Bits("b0000000??????????????????1010011") def FADD_S = Bits("b0000000??????????????????1010011")
def FSUB_S = Bits("b0000100??????????????????1010011") def FSUB_S = Bits("b0000100??????????????????1010011")
def FMUL_S = Bits("b0001000??????????????????1010011") def FMUL_S = Bits("b0001000??????????????????1010011")
@ -148,10 +146,8 @@ object Instructions
def FMAX_D = Bits("b1100101??????????000?????1010011") def FMAX_D = Bits("b1100101??????????000?????1010011")
def FMV_X_S = Bits("b111000000000?????000?????1010011") def FMV_X_S = Bits("b111000000000?????000?????1010011")
def FMV_X_D = Bits("b111000100000?????000?????1010011") def FMV_X_D = Bits("b111000100000?????000?????1010011")
def FRSR = Bits("b11101000000000000000?????1010011")
def FMV_S_X = Bits("b111100000000?????000?????1010011") def FMV_S_X = Bits("b111100000000?????000?????1010011")
def FMV_D_X = Bits("b111100100000?????000?????1010011") def FMV_D_X = Bits("b111100100000?????000?????1010011")
def FSSR = Bits("b111110000000?????000?????1010011")
def FLW = Bits("b?????????????????010?????0000111") def FLW = Bits("b?????????????????010?????0000111")
def FLD = Bits("b?????????????????011?????0000111") def FLD = Bits("b?????????????????011?????0000111")
def FSW = Bits("b?????????????????010?????0100111") def FSW = Bits("b?????????????????010?????0100111")
@ -164,7 +160,6 @@ object Instructions
def FMSUB_D = Bits("b?????01??????????????????1000111") def FMSUB_D = Bits("b?????01??????????????????1000111")
def FNMSUB_D = Bits("b?????01??????????????????1001011") def FNMSUB_D = Bits("b?????01??????????????????1001011")
def FNMADD_D = Bits("b?????01??????????????????1001111") def FNMADD_D = Bits("b?????01??????????????????1001111")
/* Automatically generated by parse-opcodes */
def CUSTOM0 = Bits("b?????????????????000?????0001011") def CUSTOM0 = Bits("b?????????????????000?????0001011")
def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011") def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011")
def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011") def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011")
@ -190,3 +185,61 @@ object Instructions
def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011") def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011")
def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011") def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
} }
object CSRs {
val fflags = 0x1
val frm = 0x2
val fcsr = 0x3
val sup0 = 0x500
val sup1 = 0x501
val epc = 0x502
val badvaddr = 0x503
val ptbr = 0x504
val asid = 0x505
val count = 0x506
val compare = 0x507
val evec = 0x508
val cause = 0x509
val status = 0x50a
val hartid = 0x50b
val impl = 0x50c
val fatc = 0x50d
val send_ipi = 0x50e
val clear_ipi = 0x50f
val stats = 0x51c
val reset = 0x51d
val tohost = 0x51e
val fromhost = 0x51f
val cycle = 0xc00
val time = 0xc01
val instret = 0xc02
val all = {
val res = collection.mutable.ArrayBuffer[Int]()
res += fflags
res += frm
res += fcsr
res += sup0
res += sup1
res += epc
res += badvaddr
res += ptbr
res += asid
res += count
res += compare
res += evec
res += cause
res += status
res += hartid
res += impl
res += fatc
res += send_ipi
res += clear_ipi
res += stats
res += reset
res += tohost
res += fromhost
res += cycle
res += time
res += instret
res.toArray
}
}

154
rocket/src/main/scala/multiplier.scala
View File

@ -2,6 +2,7 @@ package rocket
import Chisel._ import Chisel._
import ALU._ import ALU._
import Util._
class MultiplierReq(implicit conf: RocketConfiguration) extends Bundle { class MultiplierReq(implicit conf: RocketConfiguration) extends Bundle {
val fn = Bits(width = SZ_ALU_FN) val fn = Bits(width = SZ_ALU_FN)
@ -26,68 +27,113 @@ class MultiplierIO(implicit conf: RocketConfiguration) extends Bundle {
val resp = Decoupled(new MultiplierResp) val resp = Decoupled(new MultiplierResp)
} }
class Multiplier(unroll: Int = 1, earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Module { class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Module {
val io = new MultiplierIO val io = new MultiplierIO
val w = io.req.bits.in1.getWidth
val mulw = (w+mulUnroll-1)/mulUnroll*mulUnroll
val w0 = io.req.bits.in1.getWidth val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 6)
val w = (w0+1+unroll-1)/unroll*unroll val state = Reg(init=s_ready)
val cycles = w/unroll
val r_val = Reg(init=Bool(false)) val req = Reg(io.req.bits)
val r_prod = Reg(Bits(width = w*2)) val count = Reg(UInt(width = log2Up(w+1)))
val r_lsb = Reg(Bits()) val neg_out = Reg(Bool())
val r_cnt = Reg(UInt(width = log2Up(cycles+1))) val isMul = Reg(Bool())
val r_req = Reg(new MultiplierReq) val isHi = Reg(Bool())
val r_lhs = Reg(Bits(width = w0+1)) val divisor = Reg(Bits(width = w+1)) // div only needs w bits
val remainder = Reg(Bits(width = 2*mulw+2)) // div only needs 2*w+1 bits
val dw = io.req.bits.dw val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =
val fn = io.req.bits.fn DecodeLogic(io.req.bits.fn, List(X, X, X, X), List(
FN_DIV -> List(N, N, Y, Y),
FN_REM -> List(N, Y, Y, Y),
FN_DIVU -> List(N, N, N, N),
FN_REMU -> List(N, Y, N, N),
FN_MUL -> List(Y, N, X, X),
FN_MULH -> List(Y, Y, Y, Y),
FN_MULHU -> List(Y, Y, N, N),
FN_MULHSU -> List(Y, Y, Y, N)))
val lhs_msb = Mux(dw === DW_64, io.req.bits.in1(w0-1), io.req.bits.in1(w0/2-1)).toBool def sext(x: Bits, signed: Bool) = {
val lhs_sign = (isMulFN(fn, FN_MULH) || isMulFN(fn, FN_MULHSU)) && lhs_msb val sign = signed && Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1))
val lhs_hi = Mux(dw === DW_64, io.req.bits.in1(w0-1,w0/2), Fill(w0/2, lhs_sign)) val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
val lhs_in = Cat(lhs_sign, lhs_hi, io.req.bits.in1(w0/2-1,0)) (Cat(hi, x(w/2-1,0)), sign)
}
val (lhs_in, lhs_sign) = sext(io.req.bits.in1, lhsSigned)
val (rhs_in, rhs_sign) = sext(io.req.bits.in2, rhsSigned)
val rhs_msb = Mux(dw === DW_64, io.req.bits.in2(w0-1), io.req.bits.in2(w0/2-1)).toBool val subtractor = remainder(2*w,w) - divisor(w,0)
val rhs_sign = isMulFN(fn, FN_MULH) && rhs_msb val less = subtractor(w)
val rhs_hi = Mux(dw === DW_64, io.req.bits.in2(w0-1,w0/2), Fill(w0/2, rhs_sign)) val negated_remainder = -remainder(w-1,0)
val rhs_in = Cat(Fill(w-w0, rhs_sign), rhs_hi, io.req.bits.in2(w0/2-1,0))
when (state === s_neg_inputs) {
when (remainder(w-1) || isMul) {
remainder := negated_remainder
}
when (divisor(w-1) || isMul) {
divisor := subtractor
}
state := s_busy
}
when (state === s_neg_output) {
remainder := negated_remainder
state := s_done
}
when (state === s_move_rem) {
remainder := remainder(2*w, w+1)
state := Mux(neg_out, s_neg_output, s_done)
}
when (state === s_busy && isMul) {
val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
val mplier = mulReg(mulw-1,0)
val accum = mulReg(2*mulw,mulw).toSInt
val mpcand = divisor.toSInt
val prod = mplier(mulUnroll-1,0) * mpcand + accum
val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt
remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt
count := count + 1
when (count === mulw/mulUnroll-1) {
state := Mux(isHi, s_move_rem, s_done)
}
}
when (state === s_busy && !isMul) {
when (count === w) {
state := Mux(isHi, s_move_rem, Mux(neg_out, s_neg_output, s_done))
}
count := count + 1
remainder := Cat(Mux(less, remainder(2*w-1,w), subtractor(w-1,0)), remainder(w-1,0), !less)
val divisorMSB = Log2(divisor(w-1,0), w)
val dividendMSB = Log2(remainder(w-1,0), w)
val eOutPos = UInt(w-1) + divisorMSB - dividendMSB
val eOutZero = divisorMSB > dividendMSB
val eOut = count === 0 && less /* not divby0 */ && (eOutPos > 0 || eOutZero)
when (Bool(earlyOut) && eOut) {
val shift = Mux(eOutZero, UInt(w-1), eOutPos(log2Up(w)-1,0))
remainder := remainder(w-1,0) << shift
count := shift
}
when (count === 0 && !less /* divby0 */) { neg_out := false }
}
when (io.resp.fire() || io.kill) {
state := s_ready
}
when (io.req.fire()) { when (io.req.fire()) {
r_val := Bool(true) state := Mux(lhs_sign || rhs_sign && !cmdMul, s_neg_inputs, s_busy)
r_cnt := UInt(0, log2Up(cycles+1)) isMul := cmdMul
r_req := io.req.bits isHi := cmdHi
r_lhs := lhs_in count := 0
r_prod:= rhs_in neg_out := !cmdMul && Mux(cmdHi, lhs_sign, lhs_sign != rhs_sign)
r_lsb := Bool(false) divisor := Cat(rhs_sign, rhs_in)
} remainder := lhs_in
.elsewhen (io.resp.fire() || io.kill) { req := io.req.bits
r_val := Bool(false)
} }
val eOutDist = (UInt(cycles)-r_cnt)*UInt(unroll) io.resp.bits := req
val outShift = Mux(isMulFN(r_req.fn, FN_MUL), UInt(0), Mux(r_req.dw === DW_64, UInt(64), UInt(32))) io.resp.bits.data := Mux(req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
val shiftDist = Mux(r_cnt === UInt(cycles), outShift, eOutDist) io.resp.valid := state === s_done
val eOutMask = (UInt(1) << eOutDist) - UInt(1) io.req.ready := state === s_ready
val eOut = r_cnt != UInt(0) && Bool(earlyOut) && !((r_prod(w-1,0) ^ r_lsb.toSInt) & eOutMask).orR
val shift = r_prod.toSInt >> shiftDist
val sum = r_prod(2*w-1,w).toSInt + r_prod(unroll-1,0).toSInt * r_lhs.toSInt + Mux(r_lsb.toBool, r_lhs.toSInt, SInt(0))
when (r_val && (r_cnt != UInt(cycles))) {
r_lsb := r_prod(unroll-1)
r_prod := Cat(sum, r_prod(w-1,unroll)).toSInt
r_cnt := r_cnt + UInt(1)
when (eOut) {
r_prod := shift
r_cnt := UInt(cycles)
}
}
val out32 = Cat(Fill(w0/2, shift(w0/2-1)), shift(w0/2-1,0))
val out64 = shift(w0-1,0)
io.req.ready := !r_val
io.resp.bits := r_req
io.resp.bits.data := Mux(r_req.dw === DW_64, out64, out32)
io.resp.valid := r_val && (r_cnt === UInt(cycles))
} }

25
rocket/src/main/scala/nbdcache.scala
View File

@ -85,7 +85,7 @@ class StoreGen(typ: Bits, addr: Bits, dat: Bits)
dat) dat)
} }
class LoadGen(typ: Bits, addr: Bits, dat: Bits) class LoadGen(typ: Bits, addr: Bits, dat: Bits, zero: Bool)
{ {
val t = new StoreGen(typ, addr, dat) val t = new StoreGen(typ, addr, dat)
val sign = typ === MT_B || typ === MT_H || typ === MT_W || typ === MT_D val sign = typ === MT_B || typ === MT_H || typ === MT_W || typ === MT_D
@ -94,8 +94,8 @@ class LoadGen(typ: Bits, addr: Bits, dat: Bits)
val word = Cat(Mux(t.word, Fill(32, sign && wordShift(31)), dat(63,32)), wordShift) val word = Cat(Mux(t.word, Fill(32, sign && wordShift(31)), dat(63,32)), wordShift)
val halfShift = Mux(addr(1), word(31,16), word(15,0)) val halfShift = Mux(addr(1), word(31,16), word(15,0))
val half = Cat(Mux(t.half, Fill(48, sign && halfShift(15)), word(63,16)), halfShift) val half = Cat(Mux(t.half, Fill(48, sign && halfShift(15)), word(63,16)), halfShift)
val byteShift = Mux(addr(0), half(15,8), half(7,0)) val byteShift = Mux(zero, UInt(0), Mux(addr(0), half(15,8), half(7,0)))
val byte = Cat(Mux(t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift) val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
} }
class MSHRReq(implicit conf: DCacheConfig) extends HellaCacheReq { class MSHRReq(implicit conf: DCacheConfig) extends HellaCacheReq {
@ -276,7 +276,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
val meta_hazard = Reg(init=UInt(0,2)) val meta_hazard = Reg(init=UInt(0,2))
when (meta_hazard != 0) { meta_hazard := meta_hazard + 1 } when (meta_hazard != UInt(0)) { meta_hazard := meta_hazard + 1 }
when (io.meta_write.fire()) { meta_hazard := 1 } when (io.meta_write.fire()) { meta_hazard := 1 }
io.probe_rdy := !idx_match || (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && meta_hazard === 0) io.probe_rdy := !idx_match || (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && meta_hazard === 0)
@ -574,7 +574,7 @@ class MetaDataArray(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
val rst = rst_cnt < conf.sets val rst = rst_cnt < conf.sets
when (rst) { rst_cnt := rst_cnt+1 } when (rst) { rst_cnt := rst_cnt+1 }
val metabits = io.write.bits.data.state.width + conf.tagbits val metabits = io.write.bits.data.state.getWidth + conf.tagbits
val tags = Mem(UInt(width = metabits*conf.ways), conf.sets, seqRead = true) val tags = Mem(UInt(width = metabits*conf.ways), conf.sets, seqRead = true)
when (rst || io.write.valid) { when (rst || io.write.valid) {
@ -721,6 +721,7 @@ class HellaCacheExceptions extends Bundle {
class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle { class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle {
val req = Decoupled(new HellaCacheReq) val req = Decoupled(new HellaCacheReq)
val resp = Valid(new HellaCacheResp).flip val resp = Valid(new HellaCacheResp).flip
val replay_next = Valid(Bits(width = conf.reqtagbits)).flip
val xcpt = (new HellaCacheExceptions).asInput val xcpt = (new HellaCacheExceptions).asInput
val ptw = (new TLBPTWIO).flip val ptw = (new TLBPTWIO).flip
val ordered = Bool(INPUT) val ordered = Bool(INPUT)
@ -762,6 +763,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
val s1_recycled = RegEnable(s2_recycle, s1_clk_en) val s1_recycled = RegEnable(s2_recycle, s1_clk_en)
val s1_read = isRead(s1_req.cmd) val s1_read = isRead(s1_req.cmd)
val s1_write = isWrite(s1_req.cmd) val s1_write = isWrite(s1_req.cmd)
val s1_sc = s1_req.cmd === M_XSC
val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd) val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
val dtlb = Module(new TLB(8)) val dtlb = Module(new TLB(8))
@ -808,7 +810,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
val misaligned = val misaligned =
(((s1_req.typ === MT_H) || (s1_req.typ === MT_HU)) && (s1_req.addr(0) != Bits(0))) || (((s1_req.typ === MT_H) || (s1_req.typ === MT_HU)) && (s1_req.addr(0) != Bits(0))) ||
(((s1_req.typ === MT_W) || (s1_req.typ === MT_WU)) && (s1_req.addr(1,0) != Bits(0))) || (((s1_req.typ === MT_W) || (s1_req.typ === MT_WU)) && (s1_req.addr(1,0) != Bits(0))) ||
((s1_req.typ === MT_D) && (s1_req.addr(2,0) != Bits(0))); ((s1_req.typ === MT_D) && (s1_req.addr(2,0) != Bits(0)))
io.cpu.xcpt.ma.ld := s1_read && misaligned io.cpu.xcpt.ma.ld := s1_read && misaligned
io.cpu.xcpt.ma.st := s1_write && misaligned io.cpu.xcpt.ma.st := s1_write && misaligned
@ -881,7 +883,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
lrsc_count := 0 lrsc_count := 0
} }
} }
when (io.cpu.ptw.eret) { lrsc_count := 0 } when (io.cpu.ptw.sret) { lrsc_count := 0 }
val s2_data = Vec.fill(conf.ways){Bits(width = conf.bitsperrow)} val s2_data = Vec.fill(conf.ways){Bits(width = conf.bitsperrow)}
for (w <- 0 until conf.ways) { for (w <- 0 until conf.ways) {
@ -992,7 +994,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
when (s1_clk_en) { when (s1_clk_en) {
s2_store_bypass := false s2_store_bypass := false
when (bypasses.map(_._1).reduce(_||_)) { when (bypasses.map(_._1).reduce(_||_)) {
s2_store_bypass_data := PriorityMux(bypasses.map(x => (x._1, x._2))) s2_store_bypass_data := PriorityMux(bypasses)
s2_store_bypass := true s2_store_bypass := true
} }
} }
@ -1000,7 +1002,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
// load data subword mux/sign extension // load data subword mux/sign extension
val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(conf.databits))) val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(conf.databits)))
val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word) val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc)
amoalu.io := s2_req amoalu.io := s2_req
amoalu.io.lhs := s2_data_word amoalu.io.lhs := s2_data_word
@ -1034,10 +1036,13 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
io.cpu.resp.bits.has_data := isRead(s2_req.cmd) || s2_sc io.cpu.resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
io.cpu.resp.bits.replay := s2_replay io.cpu.resp.bits.replay := s2_replay
io.cpu.resp.bits.data := loadgen.word io.cpu.resp.bits.data := loadgen.word
io.cpu.resp.bits.data_subword := Mux(s2_sc, s2_sc_fail, loadgen.byte) io.cpu.resp.bits.data_subword := loadgen.byte | s2_sc_fail
io.cpu.resp.bits.store_data := s2_req.data io.cpu.resp.bits.store_data := s2_req.data
io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
io.cpu.replay_next.bits := s1_req.tag
io.mem.grant_ack <> mshrs.io.mem_finish io.mem.grant_ack <> mshrs.io.mem_finish
} }

14
rocket/src/main/scala/ptw.scala
View File

@ -17,13 +17,13 @@ class TLBPTWIO extends Bundle {
val status = new Status().asInput val status = new Status().asInput
val invalidate = Bool(INPUT) val invalidate = Bool(INPUT)
val eret = Bool(INPUT) val sret = Bool(INPUT)
} }
class DatapathPTWIO extends Bundle { class DatapathPTWIO extends Bundle {
val ptbr = UInt(INPUT, PADDR_BITS) val ptbr = UInt(INPUT, PADDR_BITS)
val invalidate = Bool(INPUT) val invalidate = Bool(INPUT)
val eret = Bool(INPUT) val sret = Bool(INPUT)
val status = new Status().asInput val status = new Status().asInput
} }
@ -83,7 +83,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
io.requestor(i).resp.bits.perm := r_pte(8,3) io.requestor(i).resp.bits.perm := r_pte(8,3)
io.requestor(i).resp.bits.ppn := resp_ppn.toUInt io.requestor(i).resp.bits.ppn := resp_ppn.toUInt
io.requestor(i).invalidate := io.dpath.invalidate io.requestor(i).invalidate := io.dpath.invalidate
io.requestor(i).eret := io.dpath.eret io.requestor(i).sret := io.dpath.sret
io.requestor(i).status := io.dpath.status io.requestor(i).status := io.dpath.status
} }
@ -91,13 +91,13 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
switch (state) { switch (state) {
is (s_ready) { is (s_ready) {
when (arb.io.out.valid) { when (arb.io.out.valid) {
state := s_req; state := s_req
} }
count := UInt(0) count := UInt(0)
} }
is (s_req) { is (s_req) {
when (io.mem.req.ready) { when (io.mem.req.ready) {
state := s_wait; state := s_wait
} }
} }
is (s_wait) { is (s_wait) {
@ -117,10 +117,10 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
} }
} }
is (s_done) { is (s_done) {
state := s_ready; state := s_ready
} }
is (s_error) { is (s_error) {
state := s_ready; state := s_ready
} }
} }
} }

28
rocket/src/main/scala/tlb.scala
View File

@ -5,30 +5,30 @@ import uncore.constants.AddressConstants._
import scala.math._ import scala.math._
class CAMIO(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle { class CAMIO(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
val clear = Bool(INPUT); val clear = Bool(INPUT)
val clear_hit = Bool(INPUT) val clear_hit = Bool(INPUT)
val tag = Bits(INPUT, tag_bits); val tag = Bits(INPUT, tag_bits)
val hit = Bool(OUTPUT); val hit = Bool(OUTPUT)
val hits = UInt(OUTPUT, entries); val hits = UInt(OUTPUT, entries)
val valid_bits = Bits(OUTPUT, entries); val valid_bits = Bits(OUTPUT, entries)
val write = Bool(INPUT); val write = Bool(INPUT)
val write_tag = Bits(INPUT, tag_bits); val write_tag = Bits(INPUT, tag_bits)
val write_addr = UInt(INPUT, addr_bits); val write_addr = UInt(INPUT, addr_bits)
} }
class RocketCAM(entries: Int, tag_bits: Int) extends Module { class RocketCAM(entries: Int, tag_bits: Int) extends Module {
val addr_bits = ceil(log(entries)/log(2)).toInt; val addr_bits = ceil(log(entries)/log(2)).toInt
val io = new CAMIO(entries, addr_bits, tag_bits); val io = new CAMIO(entries, addr_bits, tag_bits)
val cam_tags = Vec.fill(entries){Reg(Bits(width = tag_bits))} val cam_tags = Mem(Bits(width = tag_bits), entries)
val vb_array = Reg(init=Bits(0, entries)) val vb_array = Reg(init=Bits(0, entries))
when (io.write) { when (io.write) {
vb_array := vb_array.bitSet(io.write_addr, Bool(true)); vb_array := vb_array.bitSet(io.write_addr, Bool(true))
cam_tags(io.write_addr) := io.write_tag cam_tags(io.write_addr) := io.write_tag
} }
when (io.clear) { when (io.clear) {
vb_array := Bits(0, entries); vb_array := Bits(0, entries)
} }
.elsewhen (io.clear_hit) { .elsewhen (io.clear_hit) {
vb_array := vb_array & ~io.hits vb_array := vb_array & ~io.hits
@ -36,7 +36,7 @@ class RocketCAM(entries: Int, tag_bits: Int) extends Module {
val hits = (0 until entries).map(i => vb_array(i) && cam_tags(i) === io.tag) val hits = (0 until entries).map(i => vb_array(i) && cam_tags(i) === io.tag)
io.valid_bits := vb_array; io.valid_bits := vb_array
io.hits := Vec(hits).toBits io.hits := Vec(hits).toBits
io.hit := io.hits.orR io.hit := io.hits.orR
} }

19
rocket/src/main/scala/util.scala
View File

@ -9,6 +9,7 @@ object Util
implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false
implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0
implicit def booleanToBool(x: Boolean): Bits = Bool(x) implicit def booleanToBool(x: Boolean): Bits = Bool(x)
implicit def intSeqToUIntSeq(x: Iterable[Int]): Iterable[UInt] = x.map(UInt(_))
implicit def wcToUInt(c: WideCounter): UInt = c.value implicit def wcToUInt(c: WideCounter): UInt = c.value
} }
@ -27,19 +28,19 @@ object AVec
object Str object Str
{ {
def apply(s: String): Bits = { def apply(s: String): UInt = {
var i = BigInt(0) var i = BigInt(0)
require(s.forall(validChar _)) require(s.forall(validChar _))
for (c <- s) for (c <- s)
i = (i << 8) | c i = (i << 8) | c
Lit(i, s.length*8){Bits()} UInt(i, s.length*8)
} }
def apply(x: Char): Bits = { def apply(x: Char): UInt = {
require(validChar(x)) require(validChar(x))
Lit(x, 8){Bits()} UInt(x.toInt, 8)
} }
def apply(x: UInt): Bits = apply(x, 10) def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): Bits = { def apply(x: UInt, radix: Int): UInt = {
val rad = UInt(radix) val rad = UInt(radix)
val w = x.getWidth val w = x.getWidth
require(w > 0) require(w > 0)
@ -52,8 +53,8 @@ object Str
} }
s s
} }
def apply(x: SInt): Bits = apply(x, 10) def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): Bits = { def apply(x: SInt, radix: Int): UInt = {
val neg = x < SInt(0) val neg = x < SInt(0)
val abs = x.abs val abs = x.abs
if (radix != 10) { if (radix != 10) {
@ -77,7 +78,7 @@ object Str
} }
} }
private def digit(d: UInt): Bits = Mux(d < UInt(10), Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def digit(d: UInt): UInt = Mux(d < UInt(10), Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF) private def validChar(x: Char) = x == (x & 0xFF)
} }