riscv/rocket-chip
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use updated NASTI channel constructors

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This commit is contained in:
Howard Mao 2015-09-25 12:07:27 -07:00
parent 8c4ac0f4f3
commit 308022210a
2 changed files with 11 additions and 20 deletions
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29
uncore/src/main/scala/rtc.scala
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@ -18,6 +18,7 @@ class RTC(pcr_MTIME: Int) extends Module with HTIFParameters {
val sending_addr = Reg(init = Bool(false)) val sending_addr = Reg(init = Bool(false))
val sending_data = Reg(init = Bool(false)) val sending_data = Reg(init = Bool(false))
val send_acked = Reg(init = Vec(nCores, Bool(true))) val send_acked = Reg(init = Vec(nCores, Bool(true)))
val coreId = Wire(UInt(width = log2Up(nCores)))
when (rtc_tick) { when (rtc_tick) {
rtc := rtc + UInt(1) rtc := rtc + UInt(1)
@ -27,45 +28,35 @@ class RTC(pcr_MTIME: Int) extends Module with HTIFParameters {
} }
if (nCores > 1) { if (nCores > 1) {
val (core, addr_send_done) = Counter(io.aw.fire(), nCores) val (addr_send_cnt, addr_send_done) = Counter(io.aw.fire(), nCores)
val (_, data_send_done) = Counter(io.w.fire(), nCores) val (_, data_send_done) = Counter(io.w.fire(), nCores)
when (addr_send_done) { sending_addr := Bool(false) } when (addr_send_done) { sending_addr := Bool(false) }
when (data_send_done) { sending_data := Bool(false) } when (data_send_done) { sending_data := Bool(false) }
io.aw.bits.id := core coreId := addr_send_cnt
io.aw.bits.addr := addrTable(core)
} else { } else {
when (io.aw.fire()) { sending_addr := Bool(false) } when (io.aw.fire()) { sending_addr := Bool(false) }
when (io.w.fire()) { sending_addr := Bool(false) } when (io.w.fire()) { sending_addr := Bool(false) }
io.aw.bits.id := UInt(0) coreId := UInt(0)
io.aw.bits.addr := addrTable(0)
} }
when (io.b.fire()) { send_acked(io.b.bits.id) := Bool(true) } when (io.b.fire()) { send_acked(io.b.bits.id) := Bool(true) }
io.aw.valid := sending_addr io.aw.valid := sending_addr
io.aw.bits.size := UInt(3) // 8 bytes io.aw.bits := NASTIWriteAddressChannel(
io.aw.bits.len := UInt(0) id = coreId,
io.aw.bits.burst := Bits("b01") addr = addrTable(coreId),
io.aw.bits.lock := Bool(false) size = UInt(log2Up(scrDataBytes)))
io.aw.bits.cache := UInt("b0000")
io.aw.bits.prot := UInt("b000")
io.aw.bits.qos := UInt("b0000")
io.aw.bits.region := UInt("b0000")
io.aw.bits.user := UInt(0)
io.w.valid := sending_data io.w.valid := sending_data
io.w.bits.data := rtc io.w.bits := NASTIWriteDataChannel(data = rtc)
io.w.bits.strb := Bits(0x00FF)
io.w.bits.user := UInt(0)
io.w.bits.last := Bool(true)
io.b.ready := Bool(true) io.b.ready := Bool(true)
io.ar.valid := Bool(false) io.ar.valid := Bool(false)
io.r.ready := Bool(false) io.r.ready := Bool(false)
assert(!rtc_tick || send_acked.toBits.andR, assert(!rtc_tick || send_acked.reduce(_ && _),
s"Not all clocks were updated for rtc tick") s"Not all clocks were updated for rtc tick")
} }

2
uncore/src/main/scala/tilelink.scala
View File

@ -1439,8 +1439,8 @@ class NASTIIOTileLinkIOConverter extends TLModule with NASTIParameters {
len = Mux(has_data, UInt(tlDataBeats - 1), UInt(0))) len = Mux(has_data, UInt(tlDataBeats - 1), UInt(0)))
io.nasti.aw.bits := io.nasti.ar.bits io.nasti.aw.bits := io.nasti.ar.bits
io.nasti.w.bits := NASTIWriteDataChannel( io.nasti.w.bits := NASTIWriteDataChannel(
strb = io.tl.acquire.bits.wmask(),
data = io.tl.acquire.bits.data, data = io.tl.acquire.bits.data,
strb = io.tl.acquire.bits.wmask(),
last = tl_wrap_out || (io.tl.acquire.fire() && is_subblock)) last = tl_wrap_out || (io.tl.acquire.fire() && is_subblock))
when(!active_out){ when(!active_out){