From 308022210ac98929e2e0743fa435a67e1b4ee983 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 25 Sep 2015 12:07:27 -0700 Subject: [PATCH] use updated NASTI channel constructors --- uncore/src/main/scala/rtc.scala | 29 ++++++++++------------------ uncore/src/main/scala/tilelink.scala | 2 +- 2 files changed, 11 insertions(+), 20 deletions(-) diff --git a/uncore/src/main/scala/rtc.scala b/uncore/src/main/scala/rtc.scala index 6c2e72c6..ade83749 100644 --- a/uncore/src/main/scala/rtc.scala +++ b/uncore/src/main/scala/rtc.scala @@ -18,6 +18,7 @@ class RTC(pcr_MTIME: Int) extends Module with HTIFParameters { val sending_addr = Reg(init = Bool(false)) val sending_data = Reg(init = Bool(false)) val send_acked = Reg(init = Vec(nCores, Bool(true))) + val coreId = Wire(UInt(width = log2Up(nCores))) when (rtc_tick) { rtc := rtc + UInt(1) @@ -27,45 +28,35 @@ class RTC(pcr_MTIME: Int) extends Module with HTIFParameters { } if (nCores > 1) { - val (core, addr_send_done) = Counter(io.aw.fire(), nCores) + val (addr_send_cnt, addr_send_done) = Counter(io.aw.fire(), nCores) val (_, data_send_done) = Counter(io.w.fire(), nCores) when (addr_send_done) { sending_addr := Bool(false) } when (data_send_done) { sending_data := Bool(false) } - io.aw.bits.id := core - io.aw.bits.addr := addrTable(core) + coreId := addr_send_cnt } else { when (io.aw.fire()) { sending_addr := Bool(false) } when (io.w.fire()) { sending_addr := Bool(false) } - io.aw.bits.id := UInt(0) - io.aw.bits.addr := addrTable(0) + coreId := UInt(0) } when (io.b.fire()) { send_acked(io.b.bits.id) := Bool(true) } io.aw.valid := sending_addr - io.aw.bits.size := UInt(3) // 8 bytes - io.aw.bits.len := UInt(0) - io.aw.bits.burst := Bits("b01") - io.aw.bits.lock := Bool(false) - io.aw.bits.cache := UInt("b0000") - io.aw.bits.prot := UInt("b000") - io.aw.bits.qos := UInt("b0000") - io.aw.bits.region := UInt("b0000") - io.aw.bits.user := UInt(0) + io.aw.bits := NASTIWriteAddressChannel( + id = coreId, + addr = addrTable(coreId), + size = UInt(log2Up(scrDataBytes))) io.w.valid := sending_data - io.w.bits.data := rtc - io.w.bits.strb := Bits(0x00FF) - io.w.bits.user := UInt(0) - io.w.bits.last := Bool(true) + io.w.bits := NASTIWriteDataChannel(data = rtc) io.b.ready := Bool(true) io.ar.valid := Bool(false) io.r.ready := Bool(false) - assert(!rtc_tick || send_acked.toBits.andR, + assert(!rtc_tick || send_acked.reduce(_ && _), s"Not all clocks were updated for rtc tick") } diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index 859a115f..47e5f5fd 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -1439,8 +1439,8 @@ class NASTIIOTileLinkIOConverter extends TLModule with NASTIParameters { len = Mux(has_data, UInt(tlDataBeats - 1), UInt(0))) io.nasti.aw.bits := io.nasti.ar.bits io.nasti.w.bits := NASTIWriteDataChannel( - strb = io.tl.acquire.bits.wmask(), data = io.tl.acquire.bits.data, + strb = io.tl.acquire.bits.wmask(), last = tl_wrap_out || (io.tl.acquire.fire() && is_subblock)) when(!active_out){