riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

[rocket] bugfix: fixes #517

Browse Source
This commit is contained in:
Henry Cook 2017-01-18 12:48:58 -08:00
parent 4fe75965a0
commit 307f938b88
2 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/main/scala/coreplex/RocketTiles.scala
View File

@ -49,6 +49,7 @@ trait HasSynchronousRocketTilesModule extends CoreplexRISCVPlatformModule {
trait HasAsynchronousRocketTiles extends CoreplexRISCVPlatform { trait HasAsynchronousRocketTiles extends CoreplexRISCVPlatform {
val module: HasAsynchronousRocketTilesModule val module: HasAsynchronousRocketTilesModule
import rocket.AsyncRocketTile
val rocketTiles: Seq[AsyncRocketTile] = p(RocketConfigs).map { c => val rocketTiles: Seq[AsyncRocketTile] = p(RocketConfigs).map { c =>
LazyModule(new AsyncRocketTile(c)(p.alterPartial { LazyModule(new AsyncRocketTile(c)(p.alterPartial {
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0) case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)

2
src/main/scala/rocket/Tile.scala
View File

@ -61,7 +61,7 @@ class AsyncRocketTile(c: RocketConfig)(implicit p: Parameters) extends LazyModul
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = new Bundle { val io = new Bundle {
val master = masterNodes.map(_.bundleOut) val master = masterNodes.head.bundleOut // TODO fix after Chisel #366
val slave = slaveNode.map(_.bundleIn) val slave = slaveNode.map(_.bundleIn)
val hartid = UInt(INPUT, p(XLen)) val hartid = UInt(INPUT, p(XLen))
val interrupts = new TileInterrupts()(p).asInput val interrupts = new TileInterrupts()(p).asInput