From 307f938b882f56469ffdaea8bb57e2cdeeb595c9 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 18 Jan 2017 12:48:58 -0800 Subject: [PATCH] [rocket] bugfix: fixes #517 --- src/main/scala/coreplex/RocketTiles.scala | 1 + src/main/scala/rocket/Tile.scala | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/RocketTiles.scala b/src/main/scala/coreplex/RocketTiles.scala index 1286df67..6b3ab457 100644 --- a/src/main/scala/coreplex/RocketTiles.scala +++ b/src/main/scala/coreplex/RocketTiles.scala @@ -49,6 +49,7 @@ trait HasSynchronousRocketTilesModule extends CoreplexRISCVPlatformModule { trait HasAsynchronousRocketTiles extends CoreplexRISCVPlatform { val module: HasAsynchronousRocketTilesModule + import rocket.AsyncRocketTile val rocketTiles: Seq[AsyncRocketTile] = p(RocketConfigs).map { c => LazyModule(new AsyncRocketTile(c)(p.alterPartial { case SharedMemoryTLEdge => l1tol2.node.edgesIn(0) diff --git a/src/main/scala/rocket/Tile.scala b/src/main/scala/rocket/Tile.scala index 688218e4..abfecce8 100644 --- a/src/main/scala/rocket/Tile.scala +++ b/src/main/scala/rocket/Tile.scala @@ -61,7 +61,7 @@ class AsyncRocketTile(c: RocketConfig)(implicit p: Parameters) extends LazyModul lazy val module = new LazyModuleImp(this) { val io = new Bundle { - val master = masterNodes.map(_.bundleOut) + val master = masterNodes.head.bundleOut // TODO fix after Chisel #366 val slave = slaveNode.map(_.bundleIn) val hartid = UInt(INPUT, p(XLen)) val interrupts = new TileInterrupts()(p).asInput