riscv/rocket-chip
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HeaderlessTileLinkIO -> ClientTileLinkIO

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This commit is contained in:
Henry Cook
2015-04-17 16:56:53 -07:00
parent 49f1c0aa7b
commit 3048f4785a
4 changed files with 8 additions and 8 deletions
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4
rocket/src/main/scala/icache.scala
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@@ -41,7 +41,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
val io = new Bundle { val io = new Bundle {
val cpu = new CPUFrontendIO().flip val cpu = new CPUFrontendIO().flip
val ptw = new TLBPTWIO() val ptw = new TLBPTWIO()
val mem = new HeaderlessUncachedTileLinkIO val mem = new ClientUncachedTileLinkIO
} }
val btb = Module(new BTB(btb_updates_out_of_order)) val btb = Module(new BTB(btb_updates_out_of_order))
@@ -146,7 +146,7 @@ class ICache extends FrontendModule
val req = Valid(new ICacheReq).flip val req = Valid(new ICacheReq).flip
val resp = Decoupled(new ICacheResp) val resp = Decoupled(new ICacheResp)
val invalidate = Bool(INPUT) val invalidate = Bool(INPUT)
val mem = new HeaderlessUncachedTileLinkIO val mem = new ClientUncachedTileLinkIO
} }
require(isPow2(nSets) && isPow2(nWays)) require(isPow2(nSets) && isPow2(nWays))
require(isPow2(coreInstBytes)) require(isPow2(coreInstBytes))

2
rocket/src/main/scala/nbdcache.scala
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@@ -584,7 +584,7 @@ class HellaCache extends L1HellaCacheModule {
val io = new Bundle { val io = new Bundle {
val cpu = (new HellaCacheIO).flip val cpu = (new HellaCacheIO).flip
val ptw = new TLBPTWIO() val ptw = new TLBPTWIO()
val mem = new HeaderlessTileLinkIO val mem = new ClientTileLinkIO
} }
require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed

4
rocket/src/main/scala/rocc.scala
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@@ -44,8 +44,8 @@ class RoCCInterface extends Bundle
val interrupt = Bool(OUTPUT) val interrupt = Bool(OUTPUT)
// These should be handled differently, eventually // These should be handled differently, eventually
val imem = new HeaderlessUncachedTileLinkIO val imem = new ClientUncachedTileLinkIO
val dmem = new HeaderlessUncachedTileLinkIO val dmem = new ClientUncachedTileLinkIO
val iptw = new TLBPTWIO val iptw = new TLBPTWIO
val dptw = new TLBPTWIO val dptw = new TLBPTWIO
val pptw = new TLBPTWIO val pptw = new TLBPTWIO

6
rocket/src/main/scala/tile.scala
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@@ -13,8 +13,8 @@ case object BuildRoCC extends Field[Option[() => RoCC]]
abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) { abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
val io = new Bundle { val io = new Bundle {
val cached = new HeaderlessTileLinkIO val cached = new ClientTileLinkIO
val uncached = new HeaderlessUncachedTileLinkIO val uncached = new ClientUncachedTileLinkIO
val host = new HTIFIO val host = new HTIFIO
} }
} }
@@ -44,7 +44,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
// otherwise, just hookup the icache // otherwise, just hookup the icache
io.uncached <> params(BuildRoCC).map { buildItHere => io.uncached <> params(BuildRoCC).map { buildItHere =>
val rocc = buildItHere() val rocc = buildItHere()
val memArb = Module(new HeaderlessTileLinkIOArbiter(3)) val memArb = Module(new ClientTileLinkIOArbiter(3))
val dcIF = Module(new SimpleHellaCacheIF) val dcIF = Module(new SimpleHellaCacheIF)
core.io.rocc <> rocc.io core.io.rocc <> rocc.io
dcIF.io.requestor <> rocc.io.mem dcIF.io.requestor <> rocc.io.mem