From 3048f4785aaad90766b11a34553c25e8cd6aaae5 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 17 Apr 2015 16:56:53 -0700 Subject: [PATCH] HeaderlessTileLinkIO -> ClientTileLinkIO --- rocket/src/main/scala/icache.scala | 4 ++-- rocket/src/main/scala/nbdcache.scala | 2 +- rocket/src/main/scala/rocc.scala | 4 ++-- rocket/src/main/scala/tile.scala | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 4b5b9107..c07bd889 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -41,7 +41,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule val io = new Bundle { val cpu = new CPUFrontendIO().flip val ptw = new TLBPTWIO() - val mem = new HeaderlessUncachedTileLinkIO + val mem = new ClientUncachedTileLinkIO } val btb = Module(new BTB(btb_updates_out_of_order)) @@ -146,7 +146,7 @@ class ICache extends FrontendModule val req = Valid(new ICacheReq).flip val resp = Decoupled(new ICacheResp) val invalidate = Bool(INPUT) - val mem = new HeaderlessUncachedTileLinkIO + val mem = new ClientUncachedTileLinkIO } require(isPow2(nSets) && isPow2(nWays)) require(isPow2(coreInstBytes)) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 02fd750c..dc61ca04 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -584,7 +584,7 @@ class HellaCache extends L1HellaCacheModule { val io = new Bundle { val cpu = (new HellaCacheIO).flip val ptw = new TLBPTWIO() - val mem = new HeaderlessTileLinkIO + val mem = new ClientTileLinkIO } require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala index caee76e5..725a500b 100644 --- a/rocket/src/main/scala/rocc.scala +++ b/rocket/src/main/scala/rocc.scala @@ -44,8 +44,8 @@ class RoCCInterface extends Bundle val interrupt = Bool(OUTPUT) // These should be handled differently, eventually - val imem = new HeaderlessUncachedTileLinkIO - val dmem = new HeaderlessUncachedTileLinkIO + val imem = new ClientUncachedTileLinkIO + val dmem = new ClientUncachedTileLinkIO val iptw = new TLBPTWIO val dptw = new TLBPTWIO val pptw = new TLBPTWIO diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 8d53836c..ca6a86fb 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -13,8 +13,8 @@ case object BuildRoCC extends Field[Option[() => RoCC]] abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) { val io = new Bundle { - val cached = new HeaderlessTileLinkIO - val uncached = new HeaderlessUncachedTileLinkIO + val cached = new ClientTileLinkIO + val uncached = new ClientUncachedTileLinkIO val host = new HTIFIO } } @@ -44,7 +44,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) { // otherwise, just hookup the icache io.uncached <> params(BuildRoCC).map { buildItHere => val rocc = buildItHere() - val memArb = Module(new HeaderlessTileLinkIOArbiter(3)) + val memArb = Module(new ClientTileLinkIOArbiter(3)) val dcIF = Module(new SimpleHellaCacheIF) core.io.rocc <> rocc.io dcIF.io.requestor <> rocc.io.mem