HeaderlessTileLinkIO -> ClientTileLinkIO
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@ -41,7 +41,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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val io = new Bundle {
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val io = new Bundle {
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val cpu = new CPUFrontendIO().flip
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val cpu = new CPUFrontendIO().flip
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val ptw = new TLBPTWIO()
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val ptw = new TLBPTWIO()
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val mem = new HeaderlessUncachedTileLinkIO
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val mem = new ClientUncachedTileLinkIO
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}
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}
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val btb = Module(new BTB(btb_updates_out_of_order))
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val btb = Module(new BTB(btb_updates_out_of_order))
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@ -146,7 +146,7 @@ class ICache extends FrontendModule
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val req = Valid(new ICacheReq).flip
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val req = Valid(new ICacheReq).flip
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val resp = Decoupled(new ICacheResp)
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val resp = Decoupled(new ICacheResp)
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val invalidate = Bool(INPUT)
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val invalidate = Bool(INPUT)
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val mem = new HeaderlessUncachedTileLinkIO
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val mem = new ClientUncachedTileLinkIO
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}
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}
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(coreInstBytes))
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require(isPow2(coreInstBytes))
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@ -584,7 +584,7 @@ class HellaCache extends L1HellaCacheModule {
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val io = new Bundle {
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val io = new Bundle {
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val cpu = (new HellaCacheIO).flip
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val cpu = (new HellaCacheIO).flip
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val ptw = new TLBPTWIO()
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val ptw = new TLBPTWIO()
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val mem = new HeaderlessTileLinkIO
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val mem = new ClientTileLinkIO
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}
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}
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require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
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require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
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@ -44,8 +44,8 @@ class RoCCInterface extends Bundle
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val interrupt = Bool(OUTPUT)
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val interrupt = Bool(OUTPUT)
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// These should be handled differently, eventually
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// These should be handled differently, eventually
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val imem = new HeaderlessUncachedTileLinkIO
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val imem = new ClientUncachedTileLinkIO
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val dmem = new HeaderlessUncachedTileLinkIO
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val dmem = new ClientUncachedTileLinkIO
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val iptw = new TLBPTWIO
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val iptw = new TLBPTWIO
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val dptw = new TLBPTWIO
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val dptw = new TLBPTWIO
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val pptw = new TLBPTWIO
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val pptw = new TLBPTWIO
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@ -13,8 +13,8 @@ case object BuildRoCC extends Field[Option[() => RoCC]]
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abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
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abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
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val io = new Bundle {
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val io = new Bundle {
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val cached = new HeaderlessTileLinkIO
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val cached = new ClientTileLinkIO
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val uncached = new HeaderlessUncachedTileLinkIO
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val uncached = new ClientUncachedTileLinkIO
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val host = new HTIFIO
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val host = new HTIFIO
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}
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}
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}
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}
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@ -44,7 +44,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
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// otherwise, just hookup the icache
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// otherwise, just hookup the icache
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io.uncached <> params(BuildRoCC).map { buildItHere =>
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io.uncached <> params(BuildRoCC).map { buildItHere =>
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val rocc = buildItHere()
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val rocc = buildItHere()
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val memArb = Module(new HeaderlessTileLinkIOArbiter(3))
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val memArb = Module(new ClientTileLinkIOArbiter(3))
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val dcIF = Module(new SimpleHellaCacheIF)
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val dcIF = Module(new SimpleHellaCacheIF)
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core.io.rocc <> rocc.io
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core.io.rocc <> rocc.io
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dcIF.io.requestor <> rocc.io.mem
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dcIF.io.requestor <> rocc.io.mem
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