riscv/rocket-chip
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HeaderlessTileLinkIO -> ClientTileLinkIO

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This commit is contained in:
Henry Cook
2015-04-17 16:56:53 -07:00
parent 49f1c0aa7b
commit 3048f4785a
4 changed files with 8 additions and 8 deletions
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6
rocket/src/main/scala/tile.scala
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@ -13,8 +13,8 @@ case object BuildRoCC extends Field[Option[() => RoCC]]
abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
val io = new Bundle {
val cached = new HeaderlessTileLinkIO
val uncached = new HeaderlessUncachedTileLinkIO
val cached = new ClientTileLinkIO
val uncached = new ClientUncachedTileLinkIO
val host = new HTIFIO
}
}
@ -44,7 +44,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
// otherwise, just hookup the icache
io.uncached <> params(BuildRoCC).map { buildItHere =>
val rocc = buildItHere()
val memArb = Module(new HeaderlessTileLinkIOArbiter(3))
val memArb = Module(new ClientTileLinkIOArbiter(3))
val dcIF = Module(new SimpleHellaCacheIF)
core.io.rocc <> rocc.io
dcIF.io.requestor <> rocc.io.mem