riscv/rocket-chip
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HeaderlessTileLinkIO -> ClientTileLinkIO

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This commit is contained in:
Henry Cook
2015-04-17 16:56:53 -07:00
parent 49f1c0aa7b
commit 3048f4785a
4 changed files with 8 additions and 8 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -584,7 +584,7 @@ class HellaCache extends L1HellaCacheModule {
val io = new Bundle {
val cpu = (new HellaCacheIO).flip
val ptw = new TLBPTWIO()
val mem = new HeaderlessTileLinkIO
val mem = new ClientTileLinkIO
}
require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed