riscv/rocket-chip
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HeaderlessTileLinkIO -> ClientTileLinkIO

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This commit is contained in:
Henry Cook
2015-04-17 16:56:53 -07:00
parent 49f1c0aa7b
commit 3048f4785a
4 changed files with 8 additions and 8 deletions
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4
rocket/src/main/scala/icache.scala
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@@ -41,7 +41,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
val io = new Bundle {
val cpu = new CPUFrontendIO().flip
val ptw = new TLBPTWIO()
val mem = new HeaderlessUncachedTileLinkIO
val mem = new ClientUncachedTileLinkIO
}
val btb = Module(new BTB(btb_updates_out_of_order))
@@ -146,7 +146,7 @@ class ICache extends FrontendModule
val req = Valid(new ICacheReq).flip
val resp = Decoupled(new ICacheResp)
val invalidate = Bool(INPUT)
val mem = new HeaderlessUncachedTileLinkIO
val mem = new ClientUncachedTileLinkIO
}
require(isPow2(nSets) && isPow2(nWays))
require(isPow2(coreInstBytes))