riscv/rocket-chip
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rocketchip: eliminate all Knobs

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This commit is contained in:
Wesley W. Terpstra
2016-11-18 12:02:33 -08:00
parent 119ccae9af
commit 30425d1665
15 changed files with 106 additions and 264 deletions
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2
src/main/scala/rocketchip/BaseTop.scala
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@ -16,7 +16,7 @@ import coreplex._
// the following parameters will be refactored properly with TL2
case object GlobalAddrMap extends Field[AddrMap]
/** Enable or disable monitoring of Diplomatic buses */
case object TLEmitMonitors extends Field[Bool]
case object TLEmitMonitors extends Field[Boolean]
abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val p: Parameters) extends LazyModule {
// Fill in the TL1 legacy parameters; remove these once rocket/groundtest/unittest are TL2

34
src/main/scala/rocketchip/Configs.scala
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@ -19,25 +19,19 @@ import DefaultTestSuites._
import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
class BasePlatformConfig extends Config(
topDefinitions = {
(pname,site,here) => {
type PF = PartialFunction[Any,Any]
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
pname match {
//Memory Parameters
case TLEmitMonitors => true
case NExtTopInterrupts => 2
case SOCBusConfig => site(L1toL2Config)
case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
case PeripheryBusArithmetic => true
// Note that PLIC asserts that this is > 0.
case IncludeJtagDTM => false
case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4)
case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4)
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case _ => throw new CDEMatchError
}
}
(pname,site,here) => pname match {
//Memory Parameters
case TLEmitMonitors => true
case NExtTopInterrupts => 2
case SOCBusConfig => site(L1toL2Config)
case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
case PeripheryBusArithmetic => true
// Note that PLIC asserts that this is > 0.
case IncludeJtagDTM => false
case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4)
case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4)
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case _ => throw new CDEMatchError
})
class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
@ -120,8 +114,6 @@ class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ ne
class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
class DualCoreConfig extends Config(
new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)

1
src/main/scala/rocketchip/Generator.scala
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@ -77,7 +77,6 @@ object Generator extends util.GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateTestSuiteMakefrags
generateDSEConstraints
generateConfigString
generateGraphML
generateParameterDump