From 30425d16652943ba85f8c71035136998c111b878 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 18 Nov 2016 12:02:33 -0800 Subject: [PATCH] rocketchip: eliminate all Knobs --- src/main/scala/coreplex/Configs.scala | 151 ++++++------------ src/main/scala/groundtest/CacheFillTest.scala | 3 +- src/main/scala/groundtest/Configs.scala | 22 +-- src/main/scala/groundtest/Regression.scala | 20 +-- src/main/scala/groundtest/Tile.scala | 2 +- src/main/scala/rocket/rocc.scala | 2 +- src/main/scala/rocket/rocket.scala | 4 +- src/main/scala/rocket/tile.scala | 4 +- src/main/scala/rocket/tlb.scala | 5 +- src/main/scala/rocketchip/BaseTop.scala | 2 +- src/main/scala/rocketchip/Configs.scala | 34 ++-- src/main/scala/rocketchip/Generator.scala | 1 - src/main/scala/uncore/Builder.scala | 85 ---------- src/main/scala/uncore/agents/Cache.scala | 29 ++-- src/main/scala/util/GeneratorUtils.scala | 6 - 15 files changed, 106 insertions(+), 264 deletions(-) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index ea40693f..0584a681 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -18,9 +18,7 @@ import rocketchip.{GlobalAddrMap} import cde.{Parameters, Config, Dump, Knob, CDEMatchError} class BaseCoreplexConfig extends Config ( - topDefinitions = { (pname,site,here) => - type PF = PartialFunction[Any,Any] - def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname) + { (pname,site,here) => lazy val innerDataBits = site(XLen) lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits pname match { @@ -29,34 +27,26 @@ class BaseCoreplexConfig extends Config ( case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */ case ASIdBits => 7 //Params used by all caches - case NSets => findBy(CacheName) - case NWays => findBy(CacheName) - case RowBits => findBy(CacheName) - case NTLBEntries => findBy(CacheName) - case CacheIdBits => findBy(CacheName) - case SplitMetadata => findBy(CacheName) - case "L1I" => { - case NSets => Knob("L1I_SETS") //64 - case NWays => Knob("L1I_WAYS") //4 - case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat - case NTLBEntries => 8 - case CacheIdBits => 0 - case SplitMetadata => false - }:PF - case "L1D" => { - case NSets => Knob("L1D_SETS") //64 - case NWays => Knob("L1D_WAYS") //4 - case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat - case NTLBEntries => 8 - case CacheIdBits => 0 - case SplitMetadata => false - }:PF + case CacheName("L1I") => CacheConfig( + nSets = 64, + nWays = 4, + rowBits = site(L1toL2Config).beatBytes*8, + nTLBEntries = 8, + cacheIdBits = 0, + splitMetadata = false) + case CacheName("L1D") => CacheConfig( + nSets = 64, + nWays = 4, + rowBits = site(L1toL2Config).beatBytes*8, + nTLBEntries = 8, + cacheIdBits = 0, + splitMetadata = false) case ECCCode => None - case Replacer => () => new RandomReplacement(site(NWays)) + case Replacer => () => new RandomReplacement(site(site(CacheName)).nWays) //L1InstCache case BtbKey => BtbParameters() //L1DataCache - case DCacheKey => DCacheConfig(nMSHRs = site(Knob("L1D_MSHRS"))) + case DCacheKey => DCacheConfig(nMSHRs = 2) case DataScratchpadSize => 0 //L2 Memory System Params case AmoAluOperandBits => site(XLen) @@ -118,20 +108,11 @@ class BaseCoreplexConfig extends Config ( case NTiles => 1 case BroadcastConfig => BroadcastConfig() case BankedL2Config => BankedL2Config() - case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64) + case CacheBlockBytes => 64 case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) case EnableL2Logging => false case _ => throw new CDEMatchError - }}, - knobValues = { - case "NBANKS_PER_MEM_CHANNEL" => 1 - case "NTRACKERS_PER_BANK" => 4 - case "L1D_MSHRS" => 2 - case "L1D_SETS" => 64 - case "L1D_WAYS" => 4 - case "L1I_SETS" => 64 - case "L1I_WAYS" => 4 - case _ => throw new CDEMatchError + } } ) @@ -141,45 +122,34 @@ class WithNCores(n: Int) extends Config( }) class WithNBanksPerMemChannel(n: Int) extends Config( - knobValues = { - case "NBANKS_PER_MEM_CHANNEL" => n - case _ => throw new CDEMatchError + (pname, site, here) => pname match { + case BankedL2Config => site(BankedL2Config).copy(nBanksPerChannel = n) }) class WithNTrackersPerBank(n: Int) extends Config( - knobValues = { - case "NTRACKERS_PER_BANK" => n - case _ => throw new CDEMatchError + (pname, site, here) => pname match { + case BroadcastConfig => site(BroadcastConfig).copy(nTrackers = n) }) class WithDataScratchpad(n: Int) extends Config( (pname,site,here) => pname match { case DataScratchpadSize => n - case NSets if site(CacheName) == "L1D" => n / site(CacheBlockBytes) + case CacheName("L1D") => site(CacheName("L1D")).copy(nSets = n / site(CacheBlockBytes)) case _ => throw new CDEMatchError }) +// TODO: re-add L2 class WithL2Cache extends Config( (pname,site,here) => pname match { - case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB") - case "L2Bank" => { - case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) / - site(CacheBlockBytes)) / - (site(BankedL2Config).nBanks)) / - site(NWays) - case NWays => Knob("L2_WAYS") - case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat - case CacheIdBits => log2Ceil(site(BankedL2Config).nBanks) - case SplitMetadata => Knob("L2_SPLIT_METADATA") - }: PartialFunction[Any,Any] - case NAcquireTransactors => 2 - case NSecondaryMisses => 4 - case L2DirectoryRepresentation => new FullRepresentation(site(NTiles)) - case L2Replacer => () => new SeqRandom(site(NWays)) + case CacheName("L2") => CacheConfig( + nSets = 1024, + nWays = 1, + rowBits = site(L1toL2Config).beatBytes*8, + nTLBEntries = 0, + cacheIdBits = 1, + splitMetadata = false) case _ => throw new CDEMatchError - }, - knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048; case "L2_SPLIT_METADATA" => false; case _ => throw new CDEMatchError } -) + }) class WithBufferlessBroadcastHub extends Config( (pname, site, here) => pname match { @@ -198,36 +168,29 @@ class WithBufferlessBroadcastHub extends Config( * system depends on coherence between channels in any way, * DO NOT use this configuration. */ -class WithStatelessBridge extends Config ( - topDefinitions = { (pname,site,here) => pname match { +class WithStatelessBridge extends Config( + (pname,site,here) => pname match { case BankedL2Config => site(BankedL2Config).copy(coherenceManager = { case (_, _) => val pass = LazyModule(new TLBuffer(0)) (pass.node, pass.node) }) + case DCacheKey => site(DCacheKey).copy(nMSHRs = 0) case _ => throw new CDEMatchError - }}, - knobValues = { - case "L1D_MSHRS" => 0 - case _ => throw new CDEMatchError - } -) + }) class WithPLRU extends Config( (pname, site, here) => pname match { - case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays)) case _ => throw new CDEMatchError }) class WithL2Capacity(size_kb: Int) extends Config( - knobValues = { - case "L2_CAPACITY_IN_KB" => size_kb + (pname,site,here) => pname match { case _ => throw new CDEMatchError }) class WithNL2Ways(n: Int) extends Config( - knobValues = { - case "L2_WAYS" => n - case _ => throw new CDEMatchError + (pname,site,here) => pname match { + case CacheName("L2") => site(CacheName("L2")).copy(nWays = n) }) class WithRV32 extends Config( @@ -235,35 +198,26 @@ class WithRV32 extends Config( case XLen => 32 case FPUKey => Some(FPUConfig(divSqrt = false)) case _ => throw new CDEMatchError - } -) + }) -class WithBlockingL1 extends Config ( - knobValues = { - case "L1D_MSHRS" => 0 +class WithBlockingL1 extends Config( + (pname,site,here) => pname match { + case DCacheKey => site(DCacheKey).copy(nMSHRs = 0) case _ => throw new CDEMatchError - } -) + }) -class WithSmallCores extends Config ( - topDefinitions = { (pname,site,here) => pname match { +class WithSmallCores extends Config( + (pname,site,here) => pname match { case MulDivKey => Some(MulDivConfig()) case FPUKey => None case UseVM => false - case NTLBEntries => 4 case BtbKey => BtbParameters(nEntries = 0) case NAcquireTransactors => 2 + case CacheName("L1D") => site(CacheName("L1D")).copy(nSets = 64, nWays = 1, nTLBEntries = 4) + case CacheName("L1I") => site(CacheName("L1I")).copy(nSets = 64, nWays = 1, nTLBEntries = 4) + case DCacheKey => site(DCacheKey).copy(nMSHRs = 0) case _ => throw new CDEMatchError - }}, - knobValues = { - case "L1D_SETS" => 64 - case "L1D_WAYS" => 1 - case "L1I_SETS" => 64 - case "L1I_WAYS" => 1 - case "L1D_MSHRS" => 0 - case _ => throw new CDEMatchError - } -) + }) class WithRoccExample extends Config( (pname, site, here) => pname match { @@ -282,6 +236,3 @@ class WithRoccExample extends Config( case RoccMaxTaggedMemXacts => 1 case _ => throw new CDEMatchError }) - -class WithSplitL2Metadata extends Config( - knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError }) diff --git a/src/main/scala/groundtest/CacheFillTest.scala b/src/main/scala/groundtest/CacheFillTest.scala index b2298cbc..f97ce852 100644 --- a/src/main/scala/groundtest/CacheFillTest.scala +++ b/src/main/scala/groundtest/CacheFillTest.scala @@ -9,7 +9,8 @@ import cde.{Parameters, Field} class CacheFillTest(implicit p: Parameters) extends GroundTest()(p) with HasTileLinkParameters { - val capacityKb: Int = p("L2_CAPACITY_IN_KB") + val l2Config = p(CacheName("L2")) + val capacityKb = l2Config.nSets * l2Config.nWays * l2Config.rowBits / (1024*8) val nblocks = capacityKb * 1024 / p(CacheBlockBytes) val s_start :: s_prefetch :: s_retrieve :: s_finished :: Nil = Enum(Bits(), 4) val state = Reg(init = s_start) diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index 66891edd..f2da1d23 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -39,10 +39,10 @@ class MemtestStatelessConfig extends Config( class FancyMemtestConfig extends Config( new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++ new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++ - new WithSplitL2Metadata ++ new WithL2Cache ++ new GroundTestConfig) + new WithL2Cache ++ new GroundTestConfig) class CacheFillTestConfig extends Config( - new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig) + new WithNL2Ways(4) ++ new WithL2Capacity(4) ++ new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig) class BroadcastRegressionTestConfig extends Config( new WithBroadcastRegressionTest ++ new GroundTestConfig) @@ -108,10 +108,9 @@ class WithComparator extends Config( width = 8, operations = 1000, atomics = site(UseAtomics), - prefetches = site("COMPARATOR_PREFETCHES")) + prefetches = false) case FPUConfig => None case UseAtomics => false - case "COMPARATOR_PREFETCHES" => false case _ => throw new CDEMatchError }) @@ -123,7 +122,7 @@ class WithAtomics extends Config( class WithPrefetches extends Config( (pname, site, here) => pname match { - case "COMPARATOR_PREFETCHES" => true + case ComparatorKey => site(ComparatorKey).copy(prefetches = true) case _ => throw new CDEMatchError }) @@ -156,11 +155,6 @@ class WithCacheFillTest extends Config( case BuildGroundTest => (p: Parameters) => Module(new CacheFillTest()(p)) case _ => throw new CDEMatchError - }, - knobValues = { - case "L2_WAYS" => 4 - case "L2_CAPACITY_IN_KB" => 4 - case _ => throw new CDEMatchError }) class WithBroadcastRegressionTest extends Config( @@ -188,7 +182,7 @@ class WithCacheRegressionTest extends Config( }) class WithTraceGen extends Config( - topDefinitions = (pname, site, here) => pname match { + (pname, site, here) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(uncached = 1, cached = 1) } @@ -207,10 +201,6 @@ class WithTraceGen extends Config( }.flatten } case UseAtomics => true - case _ => throw new CDEMatchError - }, - knobValues = { - case "L1D_SETS" => 16 - case "L1D_WAYS" => 1 + case CacheName("L1D") => site(CacheName("L1D")).copy(nSets = 16, nWays = 1) case _ => throw new CDEMatchError }) diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala index 5bfab877..d14d5032 100644 --- a/src/main/scala/groundtest/Regression.scala +++ b/src/main/scala/groundtest/Regression.scala @@ -108,8 +108,7 @@ class PutBlockMergeRegression(implicit p: Parameters) disableCache() - val l2params = p.alterPartial({ case CacheName => "L2Bank" }) - val nSets = l2params(NSets) + val nSets = p(CacheName("L2")).nSets val addr_blocks = Vec(Seq(0, 0, nSets).map(num => UInt(num + memStartBlock))) val nSteps = addr_blocks.size val (acq_beat, acq_done) = Counter(io.mem.acquire.fire(), tlDataBeats) @@ -425,9 +424,8 @@ class SequentialSameIdGetRegression(implicit p: Parameters) extends Regression() class WritebackRegression(implicit p: Parameters) extends Regression()(p) { disableCache() - val l2params = p.alterPartial({ case CacheName => "L2Bank" }) - val nSets = l2params(NSets) - val nWays = l2params(NWays) + val nSets = p(CacheName("L2")).nSets + val nWays = p(CacheName("L2")).nWays val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(memStartBlock + i * nSets) } val data = Vec.tabulate(nWays + 1) { i => UInt((i + 1) * 1423) } @@ -478,10 +476,9 @@ class WritebackRegression(implicit p: Parameters) extends Regression()(p) { class ReleaseRegression(implicit p: Parameters) extends Regression()(p) { disableMem() - val l1params = p.alterPartial({ case CacheName => "L1D" }) - val nSets = l1params(NSets) - val nWays = l1params(NWays) - val blockOffset = l1params(CacheBlockOffsetBits) + val nSets = p(CacheName("L1D")).nSets + val nWays = p(CacheName("L1D")).nWays + val blockOffset = p(CacheBlockOffsetBits) val startBlock = memStartBlock + 10 val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(startBlock + i * nSets) } @@ -566,9 +563,8 @@ class PutBeforePutBlockRegression(implicit p: Parameters) extends Regression()(p class MergedGetRegression(implicit p: Parameters) extends Regression()(p) { disableCache() - val l2params = p.alterPartial({ case CacheName => "L2Bank" }) - val nSets = l2params(NSets) - val nWays = l2params(NWays) + val nSets = p(CacheName("L2")).nSets + val nWays = p(CacheName("L2")).nWays val (s_idle :: s_put :: s_get :: s_done :: Nil) = Enum(Bits(), 4) val state = Reg(init = s_idle) diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index 851dbff6..387fa9ac 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -101,7 +101,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module } class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGroundTestParameters { - val dcacheParams = p.alterPartial({ case CacheName => "L1D" }) + val dcacheParams = p.alterPartial({ case CacheName => CacheName("L1D") }) val slave = None val dcache = HellaCache(p(DCacheKey))(dcacheParams) val ucLegacy = LazyModule(new TLLegacy()(p)) diff --git a/src/main/scala/rocket/rocc.scala b/src/main/scala/rocket/rocc.scala index c0f9de9a..64dbdec2 100644 --- a/src/main/scala/rocket/rocc.scala +++ b/src/main/scala/rocket/rocc.scala @@ -41,7 +41,7 @@ class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) { class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) { val cmd = Decoupled(new RoCCCommand).flip val resp = Decoupled(new RoCCResponse) - val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" })) + val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => CacheName("L1D") })) val busy = Bool(OUTPUT) val interrupt = Bool(OUTPUT) diff --git a/src/main/scala/rocket/rocket.scala b/src/main/scala/rocket/rocket.scala index 0b6bcb0a..85d31dcb 100644 --- a/src/main/scala/rocket/rocket.scala +++ b/src/main/scala/rocket/rocket.scala @@ -142,8 +142,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) { val io = new Bundle { val interrupts = new TileInterrupts().asInput val hartid = UInt(INPUT, xLen) - val imem = new FrontendIO()(p.alterPartial({case CacheName => "L1I" })) - val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" })) + val imem = new FrontendIO()(p.alterPartial({case CacheName => CacheName("L1I") })) + val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => CacheName("L1D") })) val ptw = new DatapathPTWIO().flip val fpu = new FPUIO().flip val rocc = new RoCCInterface().flip diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala index aa60e7c4..0bdaf20e 100644 --- a/src/main/scala/rocket/tile.scala +++ b/src/main/scala/rocket/tile.scala @@ -25,12 +25,12 @@ case class RoccParameters( class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { val dcacheParams = p.alterPartial({ - case CacheName => "L1D" + case CacheName => CacheName("L1D") case TLId => "L1toL2" case TileId => tileId // TODO using this messes with Heirarchical P&R: change to io.hartid? }) val icacheParams = p.alterPartial({ - case CacheName => "L1I" + case CacheName => CacheName("L1I") case TLId => "L1toL2" }) diff --git a/src/main/scala/rocket/tlb.scala b/src/main/scala/rocket/tlb.scala index 8bb1e666..5f137583 100644 --- a/src/main/scala/rocket/tlb.scala +++ b/src/main/scala/rocket/tlb.scala @@ -8,15 +8,14 @@ import Chisel.ImplicitConversions._ import junctions._ import scala.math._ import cde.{Parameters, Field} -import uncore.agents.PseudoLRU +import uncore.agents._ import uncore.coherence._ case object PgLevels extends Field[Int] case object ASIdBits extends Field[Int] -case object NTLBEntries extends Field[Int] trait HasTLBParameters extends HasCoreParameters { - val entries = p(NTLBEntries) + val entries = p(p(CacheName)).nTLBEntries val camAddrBits = log2Ceil(entries) val camTagBits = asIdBits + vpnBits } diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index 453238a5..d2c066b1 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -16,7 +16,7 @@ import coreplex._ // the following parameters will be refactored properly with TL2 case object GlobalAddrMap extends Field[AddrMap] /** Enable or disable monitoring of Diplomatic buses */ -case object TLEmitMonitors extends Field[Bool] +case object TLEmitMonitors extends Field[Boolean] abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val p: Parameters) extends LazyModule { // Fill in the TL1 legacy parameters; remove these once rocket/groundtest/unittest are TL2 diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala index 848a2941..f5889c47 100644 --- a/src/main/scala/rocketchip/Configs.scala +++ b/src/main/scala/rocketchip/Configs.scala @@ -19,25 +19,19 @@ import DefaultTestSuites._ import cde.{Parameters, Config, Dump, Knob, CDEMatchError} class BasePlatformConfig extends Config( - topDefinitions = { - (pname,site,here) => { - type PF = PartialFunction[Any,Any] - def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname) - pname match { - //Memory Parameters - case TLEmitMonitors => true - case NExtTopInterrupts => 2 - case SOCBusConfig => site(L1toL2Config) - case PeripheryBusConfig => TLBusConfig(beatBytes = 4) - case PeripheryBusArithmetic => true - // Note that PLIC asserts that this is > 0. - case IncludeJtagDTM => false - case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4) - case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4) - case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock - case _ => throw new CDEMatchError - } - } + (pname,site,here) => pname match { + //Memory Parameters + case TLEmitMonitors => true + case NExtTopInterrupts => 2 + case SOCBusConfig => site(L1toL2Config) + case PeripheryBusConfig => TLBusConfig(beatBytes = 4) + case PeripheryBusArithmetic => true + // Note that PLIC asserts that this is > 0. + case IncludeJtagDTM => false + case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4) + case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4) + case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock + case _ => throw new CDEMatchError }) class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig) @@ -120,8 +114,6 @@ class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ ne class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig) -class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config) - class DualCoreConfig extends Config( new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig) diff --git a/src/main/scala/rocketchip/Generator.scala b/src/main/scala/rocketchip/Generator.scala index 28e101a3..a1eb5356 100644 --- a/src/main/scala/rocketchip/Generator.scala +++ b/src/main/scala/rocketchip/Generator.scala @@ -77,7 +77,6 @@ object Generator extends util.GeneratorApp { val longName = names.topModuleProject + "." + names.configs generateFirrtl generateTestSuiteMakefrags - generateDSEConstraints generateConfigString generateGraphML generateParameterDump diff --git a/src/main/scala/uncore/Builder.scala b/src/main/scala/uncore/Builder.scala index 624120e4..1ccbb9af 100644 --- a/src/main/scala/uncore/Builder.scala +++ b/src/main/scala/uncore/Builder.scala @@ -33,88 +33,3 @@ object UncoreBuilder extends App { pdFile.close } - -class DefaultL2Config extends Config ( - topDefinitions = { (pname,site,here) => - pname match { - case PAddrBits => 32 - case CacheId => 0 - case CacheName => "L2Bank" - case TLId => "L1toL2" - case InnerTLId => "L1toL2" - case OuterTLId => "L2toMC" - case "N_CACHED" => Dump("N_CACHED",here[Int]("CACHED_CLIENTS_PER_PORT")) - case "N_UNCACHED" => Dump("N_UNCACHED",here[Int]("MAX_CLIENTS_PER_PORT") - here[Int]("N_CACHED")) - case "MAX_CLIENT_XACTS" => 4 - case "MAX_CLIENTS_PER_PORT" => Knob("NTILES") - case "CACHED_CLIENTS_PER_PORT" => Knob("N_CACHED_TILES") - case TLKey("L1toL2") => - TileLinkParameters( - coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)), - nManagers = 1, - nCachingClients = here[Int]("N_CACHED"), - nCachelessClients = here[Int]("N_UNCACHED"), - maxClientXacts = here[Int]("MAX_CLIENT_XACTS"), - maxClientsPerPort = here[Int]("MAX_CLIENTS_PER_PORT"), - maxManagerXacts = site(NAcquireTransactors) + 2, - dataBits = site(CacheBlockBytes)*8, - dataBeats = 2) - case TLKey("L2toMC") => - TileLinkParameters( - coherencePolicy = new MEICoherence(new NullRepresentation(1)), - nManagers = 1, - nCachingClients = 1, - nCachelessClients = 0, - maxClientXacts = 1, - maxClientsPerPort = site(NAcquireTransactors) + 2, - maxManagerXacts = 1, - dataBits = site(CacheBlockBytes)*8, - dataBeats = 2) - case CacheBlockBytes => 64 - case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) - case "L2_SETS" => Knob("L2_SETS") - case NSets => Dump("L2_SETS",here[Int]("L2_SETS")) - case NWays => Knob("L2_WAYS") - case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat - case CacheIdBits => Dump("CACHE_ID_BITS",1) - case L2StoreDataQueueDepth => 1 - case NAcquireTransactors => Dump("N_ACQUIRE_TRANSACTORS",2) - case NSecondaryMisses => 4 - case L2DirectoryRepresentation => new FullRepresentation(here[Int]("N_CACHED")) - case L2Replacer => () => new SeqRandom(site(NWays)) - case ECCCode => None - case AmoAluOperandBits => 64 - case SplitMetadata => false - case _ => throw new CDEMatchError - // case XLen => 128 - }}, - knobValues = { - case "L2_WAYS" => 1 - case "L2_SETS" => 1024 - case "NTILES" => 2 - case "N_CACHED_TILES" => 2 - case "L2_CAPACITY_IN_KB" => 256 - case _ => throw new CDEMatchError - } -) - -class WithPLRU extends Config( - (pname, site, here) => pname match { - case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays)) - case _ => throw new CDEMatchError - }) - -class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config) - -class With1L2Ways extends Config(knobValues = { case "L2_WAYS" => 1; case _ => throw new CDEMatchError }) -class With2L2Ways extends Config(knobValues = { case "L2_WAYS" => 2; case _ => throw new CDEMatchError }) -class With4L2Ways extends Config(knobValues = { case "L2_WAYS" => 4; case _ => throw new CDEMatchError }) - -class With1Cached extends Config(knobValues = { case "N_CACHED_TILES" => 1; case _ => throw new CDEMatchError }) -class With2Cached extends Config(knobValues = { case "N_CACHED_TILES" => 2; case _ => throw new CDEMatchError }) - - -class W1Cached1WaysConfig extends Config(new With1L2Ways ++ new With1Cached ++ new DefaultL2Config) -class W1Cached2WaysConfig extends Config(new With2L2Ways ++ new With1Cached ++ new DefaultL2Config) -class W2Cached1WaysConfig extends Config(new With1L2Ways ++ new With2Cached ++ new DefaultL2Config) -class W2Cached2WaysConfig extends Config(new With2L2Ways ++ new With2Cached ++ new DefaultL2Config) diff --git a/src/main/scala/uncore/agents/Cache.scala b/src/main/scala/uncore/agents/Cache.scala index d0ef95cd..ac6267b7 100644 --- a/src/main/scala/uncore/agents/Cache.scala +++ b/src/main/scala/uncore/agents/Cache.scala @@ -14,36 +14,41 @@ import uncore.util._ import util._ import cde.{Parameters, Field} -case object CacheName extends Field[String] -case object NSets extends Field[Int] -case object NWays extends Field[Int] -case object RowBits extends Field[Int] +case class CacheConfig( + nSets: Int, + nWays: Int, + rowBits: Int, + nTLBEntries: Int, + cacheIdBits: Int, + splitMetadata: Boolean) +case class CacheName(id: String) extends Field[CacheConfig] +case object CacheName extends Field[CacheName] + case object Replacer extends Field[() => ReplacementPolicy] case object L2Replacer extends Field[() => SeqReplacementPolicy] case object NPrimaryMisses extends Field[Int] case object NSecondaryMisses extends Field[Int] case object CacheBlockBytes extends Field[Int] case object ECCCode extends Field[Option[Code]] -case object CacheIdBits extends Field[Int] case object CacheId extends Field[Int] -case object SplitMetadata extends Field[Boolean] trait HasCacheParameters { implicit val p: Parameters - val nSets = p(NSets) + val cacheConfig = p(p(CacheName)) + val nSets = cacheConfig.nSets val blockOffBits = p(CacheBlockOffsetBits) - val cacheIdBits = p(CacheIdBits) - val idxBits = log2Up(nSets) + val cacheIdBits = cacheConfig.cacheIdBits + val idxBits = log2Up(cacheConfig.nSets) val untagBits = blockOffBits + cacheIdBits + idxBits val tagBits = p(PAddrBits) - untagBits - val nWays = p(NWays) + val nWays = cacheConfig.nWays val wayBits = log2Up(nWays) val isDM = nWays == 1 - val rowBits = p(RowBits) + val rowBits = cacheConfig.rowBits val rowBytes = rowBits/8 val rowOffBits = log2Up(rowBytes) val code = p(ECCCode).getOrElse(new IdentityCode) - val hasSplitMetadata = p(SplitMetadata) + val hasSplitMetadata = cacheConfig.splitMetadata } abstract class CacheModule(implicit val p: Parameters) extends Module diff --git a/src/main/scala/util/GeneratorUtils.scala b/src/main/scala/util/GeneratorUtils.scala index 4227e1d1..8d607560 100644 --- a/src/main/scala/util/GeneratorUtils.scala +++ b/src/main/scala/util/GeneratorUtils.scala @@ -103,12 +103,6 @@ trait GeneratorApp extends App with HasGeneratorUtilities { TestGeneration.addSuite(DefaultTestSuites.singleRegression) } - /** Output Design Space Exploration knobs and constraints. */ - def generateDSEConstraints { - writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE - writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE - } - /** Output a global Parameter dump, which an external script can turn into Verilog headers. */ def generateParameterDump { writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()