rocketchip: eliminate all Knobs

src/main/scala/rocket/rocc.scala

@@ -41,7 +41,7 @@ class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
 class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
   val cmd = Decoupled(new RoCCCommand).flip
   val resp = Decoupled(new RoCCResponse)
-  val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
+  val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => CacheName("L1D") }))
   val busy = Bool(OUTPUT)
   val interrupt = Bool(OUTPUT)
   

src/main/scala/rocket/rocket.scala

@@ -142,8 +142,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   val io = new Bundle {
     val interrupts = new TileInterrupts().asInput
     val hartid = UInt(INPUT, xLen)
-    val imem  = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
-    val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
+    val imem  = new FrontendIO()(p.alterPartial({case CacheName => CacheName("L1I") }))
+    val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => CacheName("L1D") }))
     val ptw = new DatapathPTWIO().flip
     val fpu = new FPUIO().flip
     val rocc = new RoCCInterface().flip

src/main/scala/rocket/tile.scala

@@ -25,12 +25,12 @@ case class RoccParameters(
 
 class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
   val dcacheParams = p.alterPartial({
-    case CacheName => "L1D"
+    case CacheName => CacheName("L1D")
     case TLId => "L1toL2"
     case TileId => tileId // TODO using this messes with Heirarchical P&R: change to io.hartid?
   })
   val icacheParams = p.alterPartial({
-    case CacheName => "L1I"
+    case CacheName => CacheName("L1I")
     case TLId => "L1toL2"
   })
 

src/main/scala/rocket/tlb.scala

@@ -8,15 +8,14 @@ import Chisel.ImplicitConversions._
 import junctions._
 import scala.math._
 import cde.{Parameters, Field}
-import uncore.agents.PseudoLRU
+import uncore.agents._
 import uncore.coherence._
 
 case object PgLevels extends Field[Int]
 case object ASIdBits extends Field[Int]
-case object NTLBEntries extends Field[Int]
 
 trait HasTLBParameters extends HasCoreParameters {
-  val entries = p(NTLBEntries)
+  val entries = p(p(CacheName)).nTLBEntries
   val camAddrBits = log2Ceil(entries)
   val camTagBits = asIdBits + vpnBits
 }