riscv/rocket-chip
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rocketchip: eliminate all Knobs

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This commit is contained in:
Wesley W. Terpstra
2016-11-18 12:02:33 -08:00
parent 119ccae9af
commit 30425d1665
15 changed files with 106 additions and 264 deletions
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3
src/main/scala/groundtest/CacheFillTest.scala
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@ -9,7 +9,8 @@ import cde.{Parameters, Field}
class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
with HasTileLinkParameters {
val capacityKb: Int = p("L2_CAPACITY_IN_KB")
val l2Config = p(CacheName("L2"))
val capacityKb = l2Config.nSets * l2Config.nWays * l2Config.rowBits / (1024*8)
val nblocks = capacityKb * 1024 / p(CacheBlockBytes)
val s_start :: s_prefetch :: s_retrieve :: s_finished :: Nil = Enum(Bits(), 4)
val state = Reg(init = s_start)

22
src/main/scala/groundtest/Configs.scala
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@ -39,10 +39,10 @@ class MemtestStatelessConfig extends Config(
class FancyMemtestConfig extends Config(
new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
new WithSplitL2Metadata ++ new WithL2Cache ++ new GroundTestConfig)
new WithL2Cache ++ new GroundTestConfig)
class CacheFillTestConfig extends Config(
new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig)
new WithNL2Ways(4) ++ new WithL2Capacity(4) ++ new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig)
class BroadcastRegressionTestConfig extends Config(
new WithBroadcastRegressionTest ++ new GroundTestConfig)
@ -108,10 +108,9 @@ class WithComparator extends Config(
width = 8,
operations = 1000,
atomics = site(UseAtomics),
prefetches = site("COMPARATOR_PREFETCHES"))
prefetches = false)
case FPUConfig => None
case UseAtomics => false
case "COMPARATOR_PREFETCHES" => false
case _ => throw new CDEMatchError
})
@ -123,7 +122,7 @@ class WithAtomics extends Config(
class WithPrefetches extends Config(
(pname, site, here) => pname match {
case "COMPARATOR_PREFETCHES" => true
case ComparatorKey => site(ComparatorKey).copy(prefetches = true)
case _ => throw new CDEMatchError
})
@ -156,11 +155,6 @@ class WithCacheFillTest extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new CacheFillTest()(p))
case _ => throw new CDEMatchError
},
knobValues = {
case "L2_WAYS" => 4
case "L2_CAPACITY_IN_KB" => 4
case _ => throw new CDEMatchError
})
class WithBroadcastRegressionTest extends Config(
@ -188,7 +182,7 @@ class WithCacheRegressionTest extends Config(
})
class WithTraceGen extends Config(
topDefinitions = (pname, site, here) => pname match {
(pname, site, here) => pname match {
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(uncached = 1, cached = 1)
}
@ -207,10 +201,6 @@ class WithTraceGen extends Config(
}.flatten
}
case UseAtomics => true
case _ => throw new CDEMatchError
},
knobValues = {
case "L1D_SETS" => 16
case "L1D_WAYS" => 1
case CacheName("L1D") => site(CacheName("L1D")).copy(nSets = 16, nWays = 1)
case _ => throw new CDEMatchError
})

20
src/main/scala/groundtest/Regression.scala
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@ -108,8 +108,7 @@ class PutBlockMergeRegression(implicit p: Parameters)
disableCache()
val l2params = p.alterPartial({ case CacheName => "L2Bank" })
val nSets = l2params(NSets)
val nSets = p(CacheName("L2")).nSets
val addr_blocks = Vec(Seq(0, 0, nSets).map(num => UInt(num + memStartBlock)))
val nSteps = addr_blocks.size
val (acq_beat, acq_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
@ -425,9 +424,8 @@ class SequentialSameIdGetRegression(implicit p: Parameters) extends Regression()
class WritebackRegression(implicit p: Parameters) extends Regression()(p) {
disableCache()
val l2params = p.alterPartial({ case CacheName => "L2Bank" })
val nSets = l2params(NSets)
val nWays = l2params(NWays)
val nSets = p(CacheName("L2")).nSets
val nWays = p(CacheName("L2")).nWays
val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(memStartBlock + i * nSets) }
val data = Vec.tabulate(nWays + 1) { i => UInt((i + 1) * 1423) }
@ -478,10 +476,9 @@ class WritebackRegression(implicit p: Parameters) extends Regression()(p) {
class ReleaseRegression(implicit p: Parameters) extends Regression()(p) {
disableMem()
val l1params = p.alterPartial({ case CacheName => "L1D" })
val nSets = l1params(NSets)
val nWays = l1params(NWays)
val blockOffset = l1params(CacheBlockOffsetBits)
val nSets = p(CacheName("L1D")).nSets
val nWays = p(CacheName("L1D")).nWays
val blockOffset = p(CacheBlockOffsetBits)
val startBlock = memStartBlock + 10
val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(startBlock + i * nSets) }
@ -566,9 +563,8 @@ class PutBeforePutBlockRegression(implicit p: Parameters) extends Regression()(p
class MergedGetRegression(implicit p: Parameters) extends Regression()(p) {
disableCache()
val l2params = p.alterPartial({ case CacheName => "L2Bank" })
val nSets = l2params(NSets)
val nWays = l2params(NWays)
val nSets = p(CacheName("L2")).nSets
val nWays = p(CacheName("L2")).nWays
val (s_idle :: s_put :: s_get :: s_done :: Nil) = Enum(Bits(), 4)
val state = Reg(init = s_idle)

2
src/main/scala/groundtest/Tile.scala
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@ -101,7 +101,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
}
class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGroundTestParameters {
val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
val dcacheParams = p.alterPartial({ case CacheName => CacheName("L1D") })
val slave = None
val dcache = HellaCache(p(DCacheKey))(dcacheParams)
val ucLegacy = LazyModule(new TLLegacy()(p))