riscv/rocket-chip
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Added BuildZscale param for use in Top and makefrag generation

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This commit is contained in:
Henry Cook 2015-07-13 15:46:42 -07:00
parent 407d8e473e
commit 302cd3e638
3 changed files with 31 additions and 7 deletions
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15
src/main/scala/Configs.scala
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@ -6,6 +6,7 @@ import Chisel._
import uncore._ import uncore._
import rocket._ import rocket._
import rocket.Util._ import rocket.Util._
import zscale._
import scala.math.max import scala.math.max
import DefaultTestSuites._ import DefaultTestSuites._
@ -14,6 +15,8 @@ class DefaultConfig extends ChiselConfig (
type PF = PartialFunction[Any,Any] type PF = PartialFunction[Any,Any]
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname) def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
pname match { pname match {
//
case UseZscale => false
//HTIF Parameters //HTIF Parameters
case HTIFWidth => Dump("HTIF_WIDTH", 16) case HTIFWidth => Dump("HTIF_WIDTH", 16)
case HTIFNSCR => 64 case HTIFNSCR => 64
@ -204,6 +207,18 @@ class DefaultL2VLSIConfig extends ChiselConfig(new WithL2Cache ++ new DefaultVLS
class DefaultL2CPPConfig extends ChiselConfig(new WithL2Cache ++ new DefaultCPPConfig) class DefaultL2CPPConfig extends ChiselConfig(new WithL2Cache ++ new DefaultCPPConfig)
class DefaultL2FPGAConfig extends ChiselConfig(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig) class DefaultL2FPGAConfig extends ChiselConfig(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
class WithZscale extends ChiselConfig(
(pname,site,here) => pname match {
case BuildZscale => {
TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
(r: Bool) => Module(new Zscale(r), {case TLId => "L1ToL2"})
}
case UseZscale => true
}
)
class ZscaleConfig extends ChiselConfig(new WithZscale ++ new DefaultConfig)
class FPGAConfig extends ChiselConfig ( class FPGAConfig extends ChiselConfig (
(pname,site,here) => pname match { (pname,site,here) => pname match {
case UseBackupMemoryPort => false case UseBackupMemoryPort => false

18
src/main/scala/RocketChip.scala
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@ -67,12 +67,18 @@ class MultiChannelTopIO extends BasicTopIO with TopLevelParameters {
//TODO: Remove this wrapper once multichannel DRAM controller is provided //TODO: Remove this wrapper once multichannel DRAM controller is provided
class Top extends Module with TopLevelParameters { class Top extends Module with TopLevelParameters {
val io = new TopIO val io = new TopIO
val temp = Module(new MultiChannelTop) if(!params(UseZscale)) {
val arb = Module(new MemIOArbiter(nMemChannels)) val temp = Module(new MultiChannelTop)
arb.io.inner <> temp.io.mem val arb = Module(new MemIOArbiter(nMemChannels))
io.mem <> arb.io.outer arb.io.inner <> temp.io.mem
io.mem_backup_ctrl <> temp.io.mem_backup_ctrl io.mem <> arb.io.outer
io.host <> temp.io.host io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
io.host <> temp.io.host
} else {
val temp = Module(new ZscaleTop)
io.host <> temp.io.host
}
TestGeneration.generateMakefrag TestGeneration.generateMakefrag
} }

5
src/main/scala/ZscaleChip.scala
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@ -7,6 +7,9 @@ import uncore._
import rocket._ import rocket._
import zscale._ import zscale._
case object UseZscale extends Field[Boolean]
case object BuildZscale extends Field[(Bool) => Zscale]
class ZscaleSystem extends Module { class ZscaleSystem extends Module {
val io = new Bundle { val io = new Bundle {
val host = new HTIFIO val host = new HTIFIO
@ -18,7 +21,7 @@ class ZscaleSystem extends Module {
val corereset = new POCIIO val corereset = new POCIIO
} }
val core = Module(new Zscale(io.host.reset), {case TLId => "L1ToL2"}) val core = params(BuildZscale)(io.host.reset)
val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0) val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)