From 302cd3e6386371c03b8602f8cc757529bd1c6d9c Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Mon, 13 Jul 2015 15:46:42 -0700
Subject: [PATCH] Added BuildZscale param for use in Top and makefrag
 generation

---
 src/main/scala/Configs.scala    | 15 +++++++++++++++
 src/main/scala/RocketChip.scala | 18 ++++++++++++------
 src/main/scala/ZscaleChip.scala |  5 ++++-
 3 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 37344ce9..8dc30a22 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -6,6 +6,7 @@ import Chisel._
 import uncore._
 import rocket._
 import rocket.Util._
+import zscale._
 import scala.math.max
 import DefaultTestSuites._
 
@@ -14,6 +15,8 @@ class DefaultConfig extends ChiselConfig (
     type PF = PartialFunction[Any,Any]
     def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
     pname match {
+      //
+      case UseZscale => false
       //HTIF Parameters
       case HTIFWidth => Dump("HTIF_WIDTH", 16)
       case HTIFNSCR => 64
@@ -204,6 +207,18 @@ class DefaultL2VLSIConfig extends ChiselConfig(new WithL2Cache ++ new DefaultVLS
 class DefaultL2CPPConfig extends ChiselConfig(new WithL2Cache ++ new DefaultCPPConfig)
 class DefaultL2FPGAConfig extends ChiselConfig(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
 
+class WithZscale extends ChiselConfig(
+  (pname,site,here) => pname match {
+    case BuildZscale => {
+      TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
+      (r: Bool) => Module(new Zscale(r), {case TLId => "L1ToL2"})
+    }
+    case UseZscale => true
+  }
+)
+
+class ZscaleConfig extends ChiselConfig(new WithZscale ++ new DefaultConfig)
+
 class FPGAConfig extends ChiselConfig (
   (pname,site,here) => pname match {
     case UseBackupMemoryPort => false
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 7f4ee0f3..b8f0561d 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -67,12 +67,18 @@ class MultiChannelTopIO extends BasicTopIO with TopLevelParameters {
 //TODO: Remove this wrapper once multichannel DRAM controller is provided
 class Top extends Module with TopLevelParameters {
   val io = new TopIO
-  val temp = Module(new MultiChannelTop)
-  val arb = Module(new MemIOArbiter(nMemChannels))
-  arb.io.inner <> temp.io.mem
-  io.mem <> arb.io.outer
-  io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
-  io.host <> temp.io.host
+  if(!params(UseZscale)) {
+    val temp = Module(new MultiChannelTop)
+    val arb = Module(new MemIOArbiter(nMemChannels))
+    arb.io.inner <> temp.io.mem
+    io.mem <> arb.io.outer
+    io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
+    io.host <> temp.io.host
+  } else {
+    val temp = Module(new ZscaleTop)
+    io.host <> temp.io.host
+  }
+
   TestGeneration.generateMakefrag
 }
 
diff --git a/src/main/scala/ZscaleChip.scala b/src/main/scala/ZscaleChip.scala
index ec9beeab..0f5b9ec2 100644
--- a/src/main/scala/ZscaleChip.scala
+++ b/src/main/scala/ZscaleChip.scala
@@ -7,6 +7,9 @@ import uncore._
 import rocket._
 import zscale._
 
+case object UseZscale extends Field[Boolean]
+case object BuildZscale extends Field[(Bool) => Zscale]
+
 class ZscaleSystem extends Module {
   val io = new Bundle {
     val host = new HTIFIO
@@ -18,7 +21,7 @@ class ZscaleSystem extends Module {
     val corereset = new POCIIO
   }
 
-  val core = Module(new Zscale(io.host.reset), {case TLId => "L1ToL2"})
+  val core = params(BuildZscale)(io.host.reset)
 
   val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)