riscv/rocket-chip
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Chisel3 compatibility: use >>Int instead of >>UInt

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The latter doesn't contract widths anymore.
This commit is contained in:
Andrew Waterman 2015-08-04 13:13:44 -07:00
parent e469785f5e
commit 2ff2b43c2c
1 changed files with 3 additions and 3 deletions
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6
junctions/src/main/scala/slowio.scala
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@ -24,15 +24,15 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0).toUInt d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0).toUInt
h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16).toUInt h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16).toUInt
} }
io.divisor := hold << UInt(16) | divisor io.divisor := (hold << 16) | divisor
val count = Reg{UInt(width = log2Up(divisor_max))} val count = Reg{UInt(width = log2Up(divisor_max))}
val myclock = Reg{Bool()} val myclock = Reg{Bool()}
count := count + UInt(1) count := count + UInt(1)
val rising = count === (divisor >> UInt(1)) val rising = count === (divisor >> 1)
val falling = count === divisor val falling = count === divisor
val held = count === (divisor >> UInt(1)) + hold val held = count === (divisor >> 1) + hold
when (falling) { when (falling) {
divisor := d_shadow divisor := d_shadow