From 2ff2b43c2ceaa8f0b721ae5860c78c7b45958471 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 4 Aug 2015 13:13:44 -0700 Subject: [PATCH] Chisel3 compatibility: use >>Int instead of >>UInt The latter doesn't contract widths anymore. --- junctions/src/main/scala/slowio.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/junctions/src/main/scala/slowio.scala b/junctions/src/main/scala/slowio.scala index ae3ef249..7e926918 100644 --- a/junctions/src/main/scala/slowio.scala +++ b/junctions/src/main/scala/slowio.scala @@ -24,15 +24,15 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0).toUInt h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16).toUInt } - io.divisor := hold << UInt(16) | divisor + io.divisor := (hold << 16) | divisor val count = Reg{UInt(width = log2Up(divisor_max))} val myclock = Reg{Bool()} count := count + UInt(1) - val rising = count === (divisor >> UInt(1)) + val rising = count === (divisor >> 1) val falling = count === divisor - val held = count === (divisor >> UInt(1)) + hold + val held = count === (divisor >> 1) + hold when (falling) { divisor := d_shadow