riscv/rocket-chip
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Begin adding TLDataBeats to uncore

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This commit is contained in:
Henry Cook 2014-12-07 02:57:44 -08:00
parent 404773eb9f
commit 2f733a60db
2 changed files with 4 additions and 2 deletions
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4
uncore/src/main/scala/network.scala
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@ -25,13 +25,13 @@ class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle {
abstract class PhysicalNetwork extends Module abstract class PhysicalNetwork extends Module
class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1) extends PhysicalNetwork { class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) extends PhysicalNetwork {
val io = new BasicCrossbarIO(n, dType) val io = new BasicCrossbarIO(n, dType)
val rdyVecs = List.fill(n){Vec.fill(n)(Bool())} val rdyVecs = List.fill(n){Vec.fill(n)(Bool())}
io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => { io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count)) val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count, needsLock))
(rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => { (rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => {
arb.valid := in.valid && (in.bits.header.dst === UInt(i)) arb.valid := in.valid && (in.bits.header.dst === UInt(i))
arb.bits := in.bits arb.bits := in.bits

2
uncore/src/main/scala/tilelink.scala
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@ -10,12 +10,14 @@ case object TLAddrBits extends Field[Int]
case object TLMasterXactIdBits extends Field[Int] case object TLMasterXactIdBits extends Field[Int]
case object TLClientXactIdBits extends Field[Int] case object TLClientXactIdBits extends Field[Int]
case object TLDataBits extends Field[Int] case object TLDataBits extends Field[Int]
case object TLDataBeats extends Field[Int]
abstract trait TileLinkParameters extends UsesParameters { abstract trait TileLinkParameters extends UsesParameters {
val tlAddrBits = params(TLAddrBits) val tlAddrBits = params(TLAddrBits)
val tlClientXactIdBits = params(TLClientXactIdBits) val tlClientXactIdBits = params(TLClientXactIdBits)
val tlMasterXactIdBits = params(TLMasterXactIdBits) val tlMasterXactIdBits = params(TLMasterXactIdBits)
val tlDataBits = params(TLDataBits) val tlDataBits = params(TLDataBits)
val tlDataBeats = params(TLDataBeats)
val tlWriteMaskBits = if(tlDataBits/8 < 1) 1 else tlDataBits val tlWriteMaskBits = if(tlDataBits/8 < 1) 1 else tlDataBits
val tlSubblockAddrBits = log2Up(tlWriteMaskBits) val tlSubblockAddrBits = log2Up(tlWriteMaskBits)
val tlAtomicOpcodeBits = log2Up(NUM_XA_OPS) val tlAtomicOpcodeBits = log2Up(NUM_XA_OPS)