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tilelink2: make mask generation reusable

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This commit is contained in:
Wesley W. Terpstra 2016-10-06 00:36:38 -07:00
parent b29d34038e
commit 2f7081aeaf
2 changed files with 24 additions and 22 deletions
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24
src/main/scala/uncore/tilelink2/Edges.scala
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@ -25,28 +25,8 @@ class TLEdge(
}
}
// This gets used everywhere, so make the smallest circuit possible ...
def mask(addr_lo: UInt, lgSize: UInt): UInt = {
val lgBytes = log2Ceil(manager.beatBytes)
val sizeOH = UIntToOH(lgSize, log2Up(manager.beatBytes))
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= UInt(lgBytes), Bool(true)))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
Cat(helper(lgBytes).map(_._1).reverse)
}
def mask(addr_lo: UInt, lgSize: UInt): UInt =
maskGen(addr_lo, lgSize, manager.beatBytes)
// !!! make sure to align addr_lo for PutPartials with 0 masks
def addr_lo(mask: UInt, lgSize: UInt): UInt = {

22
src/main/scala/uncore/tilelink2/package.scala
View File

@ -17,4 +17,26 @@ package object tilelink2
if (s >= w) x else helper(s+s, x | (x << s)(w-1,0))
helper(1, x)
}
// This gets used everywhere, so make the smallest circuit possible ...
def maskGen(addr_lo: UInt, lgSize: UInt, beatBytes: Int): UInt = {
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize, log2Up(beatBytes))
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= UInt(lgBytes), Bool(true)))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
Cat(helper(lgBytes).map(_._1).reverse)
}
}