tilelink2: make mask generation reusable
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b29d34038e
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@ -25,28 +25,8 @@ class TLEdge(
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}
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}
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// This gets used everywhere, so make the smallest circuit possible ...
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def mask(addr_lo: UInt, lgSize: UInt): UInt =
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def mask(addr_lo: UInt, lgSize: UInt): UInt = {
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maskGen(addr_lo, lgSize, manager.beatBytes)
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val lgBytes = log2Ceil(manager.beatBytes)
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val sizeOH = UIntToOH(lgSize, log2Up(manager.beatBytes))
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def helper(i: Int): Seq[(Bool, Bool)] = {
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if (i == 0) {
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Seq((lgSize >= UInt(lgBytes), Bool(true)))
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} else {
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val sub = helper(i-1)
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val size = sizeOH(lgBytes - i)
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val bit = addr_lo(lgBytes - i)
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val nbit = !bit
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Seq.tabulate (1 << i) { j =>
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val (sub_acc, sub_eq) = sub(j/2)
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val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
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val acc = sub_acc || (size && eq)
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(acc, eq)
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}
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}
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}
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Cat(helper(lgBytes).map(_._1).reverse)
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}
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// !!! make sure to align addr_lo for PutPartials with 0 masks
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// !!! make sure to align addr_lo for PutPartials with 0 masks
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def addr_lo(mask: UInt, lgSize: UInt): UInt = {
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def addr_lo(mask: UInt, lgSize: UInt): UInt = {
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@ -17,4 +17,26 @@ package object tilelink2
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if (s >= w) x else helper(s+s, x | (x << s)(w-1,0))
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if (s >= w) x else helper(s+s, x | (x << s)(w-1,0))
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helper(1, x)
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helper(1, x)
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}
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}
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// This gets used everywhere, so make the smallest circuit possible ...
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def maskGen(addr_lo: UInt, lgSize: UInt, beatBytes: Int): UInt = {
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val lgBytes = log2Ceil(beatBytes)
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val sizeOH = UIntToOH(lgSize, log2Up(beatBytes))
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def helper(i: Int): Seq[(Bool, Bool)] = {
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if (i == 0) {
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Seq((lgSize >= UInt(lgBytes), Bool(true)))
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} else {
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val sub = helper(i-1)
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val size = sizeOH(lgBytes - i)
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val bit = addr_lo(lgBytes - i)
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val nbit = !bit
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Seq.tabulate (1 << i) { j =>
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val (sub_acc, sub_eq) = sub(j/2)
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val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
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val acc = sub_acc || (size && eq)
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(acc, eq)
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}
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}
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}
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Cat(helper(lgBytes).map(_._1).reverse)
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}
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}
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}
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