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Fix the Nasti to Smi Converter for single-word Nasti busses

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There's a register that tracks what word within a Nasti transaction a
Smi response cooresponds to, since Smi itself doesn't have any
multi-word stuff.  This breaks the single-word Nasti to Smi converter
due to what's essentially a 0-width wire bug: it ends up doing something
like

  word_offset_into_nasti := nasti_address(3, 3)

when "word_offset_into_nasti" should really be a 0-bit register, but due
to some log2Up block size calculation logic it's actually a 1-bit
register.  Thus, this expression ends up grabbing a bit of the address,
which causes odd addresses to get buffered incorrectly.

My fix is to just special-case the "Nasti bus width is the same as Smi
bus width" case.
This commit is contained in:
Palmer Dabbelt 2016-06-15 21:54:59 -07:00 committed by Palmer Dabbelt
parent 6055482513
commit 2f70136f90
1 changed files with 4 additions and 1 deletions
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3
junctions/src/main/scala/smi.scala
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@ -139,7 +139,10 @@ class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
} }
nBeats := io.nasti.ar.bits.len nBeats := io.nasti.ar.bits.len
addr := io.nasti.ar.bits.addr(addrOffBits - 1, byteOffBits) addr := io.nasti.ar.bits.addr(addrOffBits - 1, byteOffBits)
if (maxWordsPerBeat > 1)
recvInd := io.nasti.ar.bits.addr(wordCountBits + byteOffBits - 1, byteOffBits) recvInd := io.nasti.ar.bits.addr(wordCountBits + byteOffBits - 1, byteOffBits)
else
recvInd := UInt(0)
id := io.nasti.ar.bits.id id := io.nasti.ar.bits.id
state := s_read state := s_read
} }