From 2f70136f905fcfa5b651eb1061a91e0bd39bc50a Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Wed, 15 Jun 2016 21:54:59 -0700 Subject: [PATCH] Fix the Nasti to Smi Converter for single-word Nasti busses There's a register that tracks what word within a Nasti transaction a Smi response cooresponds to, since Smi itself doesn't have any multi-word stuff. This breaks the single-word Nasti to Smi converter due to what's essentially a 0-width wire bug: it ends up doing something like word_offset_into_nasti := nasti_address(3, 3) when "word_offset_into_nasti" should really be a 0-bit register, but due to some log2Up block size calculation logic it's actually a 1-bit register. Thus, this expression ends up grabbing a bit of the address, which causes odd addresses to get buffered incorrectly. My fix is to just special-case the "Nasti bus width is the same as Smi bus width" case. --- junctions/src/main/scala/smi.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/junctions/src/main/scala/smi.scala b/junctions/src/main/scala/smi.scala index b804e104..ce1fbe70 100644 --- a/junctions/src/main/scala/smi.scala +++ b/junctions/src/main/scala/smi.scala @@ -139,7 +139,10 @@ class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int) } nBeats := io.nasti.ar.bits.len addr := io.nasti.ar.bits.addr(addrOffBits - 1, byteOffBits) - recvInd := io.nasti.ar.bits.addr(wordCountBits + byteOffBits - 1, byteOffBits) + if (maxWordsPerBeat > 1) + recvInd := io.nasti.ar.bits.addr(wordCountBits + byteOffBits - 1, byteOffBits) + else + recvInd := UInt(0) id := io.nasti.ar.bits.id state := s_read }