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crossings: use flip not flip()

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This seems to be the more common API
This commit is contained in:
Wesley W. Terpstra
2016-10-06 20:41:21 -07:00
parent 6d6aa3eb13
commit 2f6985efd3
3 changed files with 6 additions and 6 deletions
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6
src/main/scala/util/AsyncQueue.scala
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@@ -29,13 +29,13 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int) extends Module
val bits = log2Ceil(depth)
val io = new Bundle {
// These come from the source domain
val enq = Decoupled(gen).flip()
val enq = Decoupled(gen).flip
// These cross to the sink clock domain
val ridx = UInt(INPUT, width = bits+1)
val widx = UInt(OUTPUT, width = bits+1)
val mem = Vec(depth, gen).asOutput
// Reset for the other side
val sink_reset_n = Bool().flip()
val sink_reset_n = Bool().flip
}
val mem = Reg(Vec(depth, gen)) //This does NOT need to be asynchronously reset.
@@ -65,7 +65,7 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
val widx = UInt(INPUT, width = bits+1)
val mem = Vec(depth, gen).asInput
// Reset for the other side
val source_reset_n = Bool().flip()
val source_reset_n = Bool().flip
}
val ridx = GrayCounter(bits+1, io.deq.fire())