From 2f6985efd3a919705d3ac5fce363da8f91e6663f Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 6 Oct 2016 20:41:21 -0700
Subject: [PATCH] crossings: use flip not flip()

This seems to be the more common API
---
 src/main/scala/regmapper/RegisterCrossing.scala | 4 ++--
 src/main/scala/util/AsyncQueue.scala            | 6 +++---
 src/main/scala/util/Crossing.scala              | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/regmapper/RegisterCrossing.scala b/src/main/scala/regmapper/RegisterCrossing.scala
index 3b0a4518..4f3100b6 100644
--- a/src/main/scala/regmapper/RegisterCrossing.scala
+++ b/src/main/scala/regmapper/RegisterCrossing.scala
@@ -25,7 +25,7 @@ class BusyRegisterCrossing(clock: Clock, reset: Bool)
 
 // RegField should support connecting to one of these
 class RegisterWriteIO[T <: Data](gen: T) extends Bundle {
-  val request  = Decoupled(gen).flip()
+  val request  = Decoupled(gen).flip
   val response = Irrevocable(Bool()) // ignore .bits
 }
 
@@ -85,7 +85,7 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
 
 // RegField should support connecting to one of these
 class RegisterReadIO[T <: Data](gen: T) extends Bundle {
-  val request  = Decoupled(Bool()).flip() // ignore .bits
+  val request  = Decoupled(Bool()).flip // ignore .bits
   val response = Irrevocable(gen)
 }
 
diff --git a/src/main/scala/util/AsyncQueue.scala b/src/main/scala/util/AsyncQueue.scala
index ed035150..3061ec39 100644
--- a/src/main/scala/util/AsyncQueue.scala
+++ b/src/main/scala/util/AsyncQueue.scala
@@ -29,13 +29,13 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int) extends Module
   val bits = log2Ceil(depth)
   val io = new Bundle {
     // These come from the source domain
-    val enq  = Decoupled(gen).flip()
+    val enq  = Decoupled(gen).flip
     // These cross to the sink clock domain
     val ridx = UInt(INPUT,  width = bits+1)
     val widx = UInt(OUTPUT, width = bits+1)
     val mem  = Vec(depth, gen).asOutput
     // Reset for the other side
-    val sink_reset_n = Bool().flip()
+    val sink_reset_n = Bool().flip
   }
 
   val mem = Reg(Vec(depth, gen)) //This does NOT need to be asynchronously reset.
@@ -65,7 +65,7 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
     val widx = UInt(INPUT,  width = bits+1)
     val mem  = Vec(depth, gen).asInput
     // Reset for the other side
-    val source_reset_n = Bool().flip()
+    val source_reset_n = Bool().flip
   }
 
   val ridx = GrayCounter(bits+1, io.deq.fire())
diff --git a/src/main/scala/util/Crossing.scala b/src/main/scala/util/Crossing.scala
index ade91747..f466dc11 100644
--- a/src/main/scala/util/Crossing.scala
+++ b/src/main/scala/util/Crossing.scala
@@ -7,7 +7,7 @@ class CrossingIO[T <: Data](gen: T) extends Bundle {
   // Enqueue clock domain
   val enq_clock = Clock(INPUT)
   val enq_reset = Bool(INPUT) // synchronously deasserted wrt. enq_clock
-  val enq = Decoupled(gen).flip()
+  val enq = Decoupled(gen).flip
   // Dequeue clock domain
   val deq_clock = Clock(INPUT)
   val deq_reset = Bool(INPUT) // synchronously deasserted wrt. deq_clock