riscv/rocket-chip
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Don't use a pipe queue on D$ TL A-channel

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This cuts an I$->D$ path.
This commit is contained in:
Andrew Waterman 2017-08-01 15:17:07 -07:00
parent f988b91575
commit 2ecea2ef60
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/DCache.scala
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@ -89,7 +89,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0 val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0
val tl_out_a = Wire(tl_out.a) val tl_out_a = Wire(tl_out.a)
tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true, pipe = true)) tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true))
val tl_out_c = Wire(tl_out.c) val tl_out_c = Wire(tl_out.c)
tl_out.c <> (if (cacheParams.acquireBeforeRelease) Queue(tl_out_c, cacheDataBeats, flow = true) else tl_out_c) tl_out.c <> (if (cacheParams.acquireBeforeRelease) Queue(tl_out_c, cacheDataBeats, flow = true) else tl_out_c)