From 2ecea2ef602cba5578330eb24c7163a304217d8f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 1 Aug 2017 15:17:07 -0700 Subject: [PATCH] Don't use a pipe queue on D$ TL A-channel This cuts an I$->D$ path. --- src/main/scala/rocket/DCache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 223fade9..88c77b47 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -89,7 +89,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0 val tl_out_a = Wire(tl_out.a) - tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true, pipe = true)) + tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true)) val tl_out_c = Wire(tl_out.c) tl_out.c <> (if (cacheParams.acquireBeforeRelease) Queue(tl_out_c, cacheDataBeats, flow = true) else tl_out_c)