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Cope with changes to AddrMap

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This commit is contained in:
Andrew Waterman 2016-06-03 13:47:40 -07:00
parent f1745bf142
commit 2e88ffc364
1 changed files with 12 additions and 19 deletions
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31
uncore/src/main/scala/interconnect.scala
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@ -258,36 +258,29 @@ abstract class TileLinkInterconnect(implicit p: Parameters) extends TLModule()(p
lazy val io = new TileLinkInterconnectIO(nInner, nOuter) lazy val io = new TileLinkInterconnectIO(nInner, nOuter)
} }
class TileLinkRecursiveInterconnect( class TileLinkRecursiveInterconnect(val nInner: Int, addrMap: AddrMap)
val nInner: Int, addrmap: AddrMap, base: BigInt)
(implicit p: Parameters) extends TileLinkInterconnect()(p) { (implicit p: Parameters) extends TileLinkInterconnect()(p) {
val levelSize = addrmap.size def port(name: String) = io.out(addrMap.port(name))
val nOuter = addrmap.countSlaves val nOuter = addrMap.numSlaves
val routeSel = (addr: UInt) =>
Cat(addrMap.entries.map(e => addrMap(e.name).containsAddress(addr)).reverse)
val addrHashMap = new AddrHashMap(addrmap, base) val xbar = Module(new ClientUncachedTileLinkIOCrossbar(nInner, addrMap.length, routeSel))
val routeSel = (addr: UInt) => {
Cat(addrmap.map { case entry =>
val hashEntry = addrHashMap(entry.name)
addr >= UInt(hashEntry.start) && addr < UInt(hashEntry.start + hashEntry.region.size)
}.reverse)
}
val xbar = Module(new ClientUncachedTileLinkIOCrossbar(nInner, levelSize, routeSel))
xbar.io.in <> io.in xbar.io.in <> io.in
io.out <> addrmap.zip(xbar.io.out).flatMap { io.out <> addrMap.entries.zip(xbar.io.out).flatMap {
case (entry, xbarOut) => { case (entry, xbarOut) => {
entry.region match { entry.region match {
case _: MemSize => case submap: AddrMap if submap.isEmpty =>
Some(xbarOut)
case MemSubmap(_, submap) if submap.isEmpty =>
xbarOut.acquire.ready := Bool(false) xbarOut.acquire.ready := Bool(false)
xbarOut.grant.valid := Bool(false) xbarOut.grant.valid := Bool(false)
None None
case MemSubmap(_, submap) => case submap: AddrMap =>
val ic = Module(new TileLinkRecursiveInterconnect(1, submap, addrHashMap(entry.name).start)) val ic = Module(new TileLinkRecursiveInterconnect(1, submap))
ic.io.in.head <> xbarOut ic.io.in.head <> xbarOut
ic.io.out ic.io.out
case _ =>
Some(xbarOut)
} }
} }
} }