From 2e88ffc3644f1f6035221853799f15b469474d44 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 3 Jun 2016 13:47:40 -0700 Subject: [PATCH] Cope with changes to AddrMap --- uncore/src/main/scala/interconnect.scala | 31 +++++++++--------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/uncore/src/main/scala/interconnect.scala b/uncore/src/main/scala/interconnect.scala index c9fdb478..eb9773a1 100644 --- a/uncore/src/main/scala/interconnect.scala +++ b/uncore/src/main/scala/interconnect.scala @@ -258,36 +258,29 @@ abstract class TileLinkInterconnect(implicit p: Parameters) extends TLModule()(p lazy val io = new TileLinkInterconnectIO(nInner, nOuter) } -class TileLinkRecursiveInterconnect( - val nInner: Int, addrmap: AddrMap, base: BigInt) +class TileLinkRecursiveInterconnect(val nInner: Int, addrMap: AddrMap) (implicit p: Parameters) extends TileLinkInterconnect()(p) { - val levelSize = addrmap.size - val nOuter = addrmap.countSlaves + def port(name: String) = io.out(addrMap.port(name)) + val nOuter = addrMap.numSlaves + val routeSel = (addr: UInt) => + Cat(addrMap.entries.map(e => addrMap(e.name).containsAddress(addr)).reverse) - val addrHashMap = new AddrHashMap(addrmap, base) - val routeSel = (addr: UInt) => { - Cat(addrmap.map { case entry => - val hashEntry = addrHashMap(entry.name) - addr >= UInt(hashEntry.start) && addr < UInt(hashEntry.start + hashEntry.region.size) - }.reverse) - } - - val xbar = Module(new ClientUncachedTileLinkIOCrossbar(nInner, levelSize, routeSel)) + val xbar = Module(new ClientUncachedTileLinkIOCrossbar(nInner, addrMap.length, routeSel)) xbar.io.in <> io.in - io.out <> addrmap.zip(xbar.io.out).flatMap { + io.out <> addrMap.entries.zip(xbar.io.out).flatMap { case (entry, xbarOut) => { entry.region match { - case _: MemSize => - Some(xbarOut) - case MemSubmap(_, submap) if submap.isEmpty => + case submap: AddrMap if submap.isEmpty => xbarOut.acquire.ready := Bool(false) xbarOut.grant.valid := Bool(false) None - case MemSubmap(_, submap) => - val ic = Module(new TileLinkRecursiveInterconnect(1, submap, addrHashMap(entry.name).start)) + case submap: AddrMap => + val ic = Module(new TileLinkRecursiveInterconnect(1, submap)) ic.io.in.head <> xbarOut ic.io.out + case _ => + Some(xbarOut) } } }