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tilelink: Error device supports Acquire

We need this if we want to divert traffic to it from a TL-C slave.
This commit is contained in:
Wesley W. Terpstra 2017-07-27 11:10:34 -07:00
parent 651da73d89
commit 2e4f1611ed
4 changed files with 59 additions and 30 deletions

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@ -98,10 +98,10 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
val node = AXI4InputNode() val node = AXI4InputNode()
val xbar = LazyModule(new TLXbar) val xbar = LazyModule(new TLXbar)
val ram = LazyModule(new TLRAM(fuzzAddr)) val ram = LazyModule(new TLRAM(fuzzAddr))
val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff))))) val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256)))
ram.node := TLFragmenter(4, 16)(xbar.node) ram.node := TLFragmenter(4, 16)(xbar.node)
error.node := TLFragmenter(4, 16)(xbar.node) error.node := xbar.node
xbar.node := xbar.node :=
TLFIFOFixer()( TLFIFOFixer()(

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@ -36,6 +36,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
val toMemoryBus: TLOutwardNode = outwardNode val toMemoryBus: TLOutwardNode = outwardNode
val toSlave: TLOutwardNode = outwardNode
def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = { def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = {
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync)) val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
inwardNode :=* sink.node inwardNode :=* sink.node

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@ -4,13 +4,13 @@ package freechips.rocketchip.devices.tilelink
import Chisel._ import Chisel._
import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasPeripheryBus import freechips.rocketchip.coreplex.HasSystemBus
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import scala.math.min import scala.math.min
case class ErrorParams(address: Seq[AddressSet]) case class ErrorParams(address: Seq[AddressSet], maxTransfer: Int = 4096)
case object ErrorParams extends Field[ErrorParams] case object ErrorParams extends Field[ErrorParams]
/** Adds a /dev/null slave that generates TL error response messages */ /** Adds a /dev/null slave that generates TL error response messages */
@ -20,18 +20,23 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
val device = new SimpleDevice("error-device", Seq("sifive,error0")) val device = new SimpleDevice("error-device", Seq("sifive,error0"))
val xfer = TransferSizes(1, params.maxTransfer)
val node = TLManagerNode(Seq(TLManagerPortParameters( val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters( Seq(TLManagerParameters(
address = address, address = address,
resources = device.reg("mem"), resources = device.reg("mem"),
supportsGet = TransferSizes(1, beatBytes), regionType = RegionType.UNCACHED,
supportsPutPartial = TransferSizes(1, beatBytes), supportsAcquireT = xfer,
supportsPutFull = TransferSizes(1, beatBytes), supportsAcquireB = xfer,
supportsArithmetic = TransferSizes(1, beatBytes), supportsGet = xfer,
supportsLogical = TransferSizes(1, beatBytes), supportsPutPartial = xfer,
supportsHint = TransferSizes(1, beatBytes), supportsPutFull = xfer,
supportsArithmetic = xfer,
supportsLogical = xfer,
supportsHint = xfer,
fifoId = Some(0))), // requests are handled in order fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes, beatBytes = beatBytes,
endSinkId = 1, // can receive GrantAck
minLatency = 1))) // no bypass needed for this device minLatency = 1))) // no bypass needed for this device
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
@ -40,35 +45,57 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
} }
import TLMessages._ import TLMessages._
val opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck) import TLPermissions._
val edge = node.edgesIn(0)
val in = io.in(0) val in = io.in(0)
val a = Queue(in.a, 1) val a = Queue(in.a, 1)
val d = in.d val c = Queue(in.c, 1)
val da = Wire(in.d)
val dc = Wire(in.d)
a.ready := d.ready val a_last = edge.last(a)
d.valid := a.valid val c_last = edge.last(c)
d.bits.opcode := opcodes(a.bits.opcode) val da_last = edge.last(da)
d.bits.param := UInt(0) val dc_last = edge.last(dc)
d.bits.size := a.bits.size
d.bits.source := a.bits.source
d.bits.sink := UInt(0)
d.bits.data := UInt(0)
d.bits.error := a.bits.opcode =/= Hint // Hints may not error
// Tie off unused channels a.ready := (da.ready && da_last) || !a_last
da.valid := a.valid && a_last
val a_opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant)
da.bits.opcode := a_opcodes(a.bits.opcode)
da.bits.param := UInt(0)
da.bits.size := a.bits.size
da.bits.source := a.bits.source
da.bits.sink := UInt(0)
da.bits.data := UInt(0)
da.bits.error := Bool(true)
c.ready := (dc.ready && dc_last) || !c_last
dc.valid := c.valid && c_last
dc.bits.opcode := ReleaseAck
dc.bits.param := Vec(toN, toN, toB)(c.bits.param)
dc.bits.size := c.bits.size
dc.bits.source := c.bits.source
dc.bits.sink := UInt(0)
dc.bits.data := UInt(0)
dc.bits.error := Bool(true)
// Combine response channels
TLArbiter.lowest(edge, in.d, dc, da)
// We never probe or issue B requests; we are UNCACHED
in.b.valid := Bool(false) in.b.valid := Bool(false)
in.c.ready := Bool(true)
// Sink GrantAcks
in.e.ready := Bool(true) in.e.ready := Bool(true)
} }
} }
trait HasPeripheryErrorSlave extends HasPeripheryBus { trait HasSystemErrorSlave extends HasSystemBus {
private val params = p(ErrorParams) private val params = p(ErrorParams)
private val maxXfer = min(params.address.map(_.alignment).max.toInt, 4096) val error = LazyModule(new TLError(params, sbus.beatBytes))
val error = LazyModule(new TLError(params, pbus.beatBytes))
// Most slaves do not support a 4kB burst so this slave ends up with many more source bits than others; error.node := sbus.toSlave
// we exclude the onerously large TLMonitor that results.
error.node connectButDontMonitor pbus.toLargeBurstSlave(maxXfer)
} }

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@ -14,7 +14,7 @@ class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex
with HasMasterAXI4MMIOPort with HasMasterAXI4MMIOPort
with HasSlaveAXI4Port with HasSlaveAXI4Port
with HasPeripheryBootROM with HasPeripheryBootROM
with HasPeripheryErrorSlave { with HasSystemErrorSlave {
override lazy val module = new ExampleRocketSystemModule(this) override lazy val module = new ExampleRocketSystemModule(this)
} }