riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Cache utility traits. Completely compiles, asm tests hang.

Browse Source
This commit is contained in:
Henry Cook
2014-08-11 18:36:23 -07:00
parent ca5f38ff26
commit 2de268b3b1
8 changed files with 281 additions and 267 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/ptw.scala
View File

@ -71,7 +71,7 @@ class PTW(n: Int) extends Module
val resp_val = state === s_done || state === s_error
val resp_err = state === s_error || state === s_wait
val r_resp_ppn = io.mem.req.bits.addr >> params(PgIdxBits)
val r_resp_ppn = io.mem.req.bits.addr >> UInt(params(PgIdxBits))
val resp_ppn = Vec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count)
for (i <- 0 until io.requestor.size) {