riscv/rocket-chip
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cleaned up finish counter

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This commit is contained in:
Henry Cook 2015-03-17 19:33:05 -07:00
parent 9de5161d7a
commit 2d3f947a9c
1 changed files with 4 additions and 6 deletions
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10
uncore/src/main/scala/cache.scala
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@ -632,7 +632,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
ignt_q.io.deq.ready := ignt_data_done ignt_q.io.deq.ready := ignt_data_done
val ifin_cnt = Reg(init = UInt(0, width = log2Up(nSecondaryMisses+1))) val ifin_cnt = Reg(init = UInt(0, width = log2Up(nSecondaryMisses+1)))
when(ignt_data_done) { ifin_cnt := ifin_cnt + UInt(1) } when(ignt_data_done) { ifin_cnt := ifin_cnt + Mux(io.inner.finish.fire(), UInt(0), UInt(1)) }
.elsewhen(io.inner.finish.fire()) { ifin_cnt := ifin_cnt - UInt(1) }
val pending_reads = Reg(init=Bits(0, width = innerDataBeats)) val pending_reads = Reg(init=Bits(0, width = innerDataBeats))
pending_reads := (pending_reads | pending_reads := (pending_reads |
addPendingBit(io.inner.acquire)) & addPendingBit(io.inner.acquire)) &
@ -943,12 +945,10 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
Mux(io.ignt().requiresAck(), s_inner_finish, s_idle)) Mux(io.ignt().requiresAck(), s_inner_finish, s_idle))
} }
io.inner.finish.ready := Bool(true) io.inner.finish.ready := Bool(true)
when(io.inner.finish.valid) {
ifin_cnt := ifin_cnt - Mux(ignt_data_done, UInt(0), UInt(1))
}
} }
is(s_meta_write) { is(s_meta_write) {
io.meta.write.valid := Bool(true) io.meta.write.valid := Bool(true)
io.inner.finish.ready := Bool(true)
when(io.meta.write.ready) { when(io.meta.write.ready) {
state := Mux(io.ignt().requiresAck(), s_inner_finish, s_idle) state := Mux(io.ignt().requiresAck(), s_inner_finish, s_idle)
} }
@ -956,14 +956,12 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
is(s_inner_finish) { is(s_inner_finish) {
io.inner.finish.ready := Bool(true) io.inner.finish.ready := Bool(true)
when(io.inner.finish.valid) { when(io.inner.finish.valid) {
ifin_cnt := ifin_cnt - UInt(1)
when(ifin_cnt <= UInt(1)) { state := s_idle } when(ifin_cnt <= UInt(1)) { state := s_idle }
} }
when(ifin_cnt === UInt(0)) { state := s_idle } when(ifin_cnt === UInt(0)) { state := s_idle }
} }
} }
// Handle Get and Put merging // Handle Get and Put merging
when(io.inner.acquire.fire() && io.iacq().hasData()) { when(io.inner.acquire.fire() && io.iacq().hasData()) {
val beat = io.iacq().addr_beat val beat = io.iacq().addr_beat