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make CLOCK_PERIOD actually be the clock period, instead of half of the clock period

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Scott Johnson
2016-08-19 14:44:48 -07:00
parent 4dbcc568dc
commit 2d12f6689c
2 changed files with 2 additions and 2 deletions
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vsim/Makefrag
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@ -39,7 +39,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
$(RISCV)/lib/libfesvr.so \
-sverilog \
+incdir+$(generated_dir) \
+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
+define+RANDOMIZE \